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CompactFlash IDE (ATA) emulation speed is usually specified in "x" ratings, e.g. 8x, 20x, 133x. This is the same system used for CD-ROMs and indicates the maximum transfer rate in the form of a multiplier based on the original audio CD data transfer rate, which is 150 kB/s.
I/O Acceleration Technology (I/OAT) is a DMA engine (an embedded DMA controller) by Intel bundled with high-end server motherboards, that offloads memory copies from the main processor by performing direct memory accesses (DMA). It is typically used for accelerating network traffic, but supports any kind of copy.
An attacker could, for example, use a social engineering attack and send a "lucky winner" a rogue Thunderbolt device. Upon connecting to a computer, the device, through its direct and unimpeded access to the physical address space, would be able to bypass almost all security measures of the OS and have the ability to read encryption keys, install malware, or control other system devices.
The IBM PC took a more conventional approach, their adaptor card could support up to four drives; on the PC direct memory access (DMA) to the drives was performed using DMA channel 2 and IRQ 6. The diagram below shows a conventional floppy disk controller which communicates with the CPU via an Industry Standard Architecture (ISA) bus or similar ...
Memory-mapped I/O is preferred in IA-32 and x86-64 based architectures because the instructions that perform port-based I/O are limited to one register: EAX, AX, and AL are the only registers that data can be moved into or out of, and either a byte-sized immediate value in the instruction or a value in register DX determines which port is the source or destination port of the transfer.
Under the Amiga architecture, the direct memory access (DMA) controller is integrated into the Agnus (Alice on AGA models) chip. Both the CPU and other members of the chipset have to arbitrate for access to shared RAM via Agnus. This allows the custom chips to perform video, audio, or other DMA operations independently of the CPU.
HP 3000 Series III. The HP 3000 series [1] is a family of 16-bit and 32-bit minicomputers from Hewlett-Packard. [2] It was designed to be the first minicomputer with full support for time-sharing in the hardware and the operating system, features that had mostly been limited to mainframes, or retrofitted to existing systems like Digital's PDP-11, on which Unix was implemented.
To overcome these shortcomings, the 16550 series UARTs incorporated a 16-byte FIFO buffer with a programmable interrupt trigger of 1, 4, 8, or 14 bytes. The 16550 also incorporates a transmit FIFO, though this feature is less critical as delays in interrupt service would only result in sub-optimal transmission speeds and not actual data loss.