Search results
Results from the WOW.Com Content Network
The integer register file has 32 64-bit entries. As the SPARC ISA uses register windows , of which the UltraSPARC has eight, the actual number of registers is 144. The register file has seven read and three write ports.
OpenSPARC is an open-source hardware project, started in December 2005, for CPUs implementing the SPARC instruction architecture. The initial contribution to the project was Sun Microsystems' register-transfer level (RTL) Verilog code for a full 64-bit, 32-thread microprocessor, the UltraSPARC T1 processor.
Sun Microsystems' UltraSPARC T2 microprocessor is a multithreading, multi-core CPU. It is a member of the SPARC family, and the successor to the UltraSPARC T1 . The chip is sometimes referred to by its codename, Niagara 2 .
S1, a 64-bit Wishbone compliant CPU core based on the OpenSPARC T1 design. It is a single UltraSPARC V9 core capable of 4-way SMT. Like the T1, the source code is licensed under the GPL. OpenSPARC T2, released in 2008, a 64-bit, 64-thread implementation conforming to the UltraSPARC Architecture 2007 and to SPARC Version 9 (Level 1). Source code ...
UltraSPARC IIe Sun UltraSPARC IIe (back side). The UltraSPARC IIe "Hummingbird" was an embedded version introduced in 2000 that operated at 400 to 500 MHz, fabricated in a 0.18 μm process with aluminium interconnects.
POWER8, 64-bit, hex or twelve core, 8 way SMT/core, 5.0 GHz, follows the Power ISA 2.07. Introduced in 2014. POWER9, 64-bit, PowerNV 24 cores of 4 way SMT/core, PowerVM 12 cores of 8 way SMT/core, follows the Power ISA 3.0. Introduced in 2016. Power10, 64-bit, 15 SMT8 or 30 SMT4 cores, will follow the Power ISA 3.1. Introduced in 2021.
1× 3.5" SATA or 2× 2.5" SAS: March 2006 Sun Fire T2000 2 1× UltraSPARC T1 1.0 GHz 64 GB 4× 2.5" SAS December 2005 SPARC Enterprise T5120 1 1× UltraSPARC T2: 1.2, 1.4 GHz 128 GB 8× 2.5" SAS November 2007 SPARC Enterprise T5140 1 2× UltraSPARC T2 Plus: 1.2, 1.4 GHz 128 GB 8× 2.5" SAS April 2008 SPARC Enterprise T5220 2 1× UltraSPARC T2
Dual 375 MHz IBM POWER3-II processors on the CPU module of a RS/6000 44P 270. The POWER3 is a microprocessor, designed and exclusively manufactured by IBM, that implemented the 64-bit version of the PowerPC instruction set architecture (ISA), including all of the optional instructions of the ISA (at the time) such as instructions present in the POWER2 version of the POWER ISA but not in the ...