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Off-package cache solved the Pentium Pro's low yield issues, allowing Intel to introduce the Pentium II at a mainstream price level. [7] [8] Intel improved 16-bit code execution performance on the Pentium II, an area in which the Pentium Pro was at a notable handicap, by adding segment register caches. Most consumer software of the day was ...
System-on-a-chip based on the Pentium II. Cancelled. [61] Reference unknown; see Timna for possibilities. 1999 Tolapai: SoC Intel EP80579, a system-on-a-chip based on the 90 nm Dothan Pentium M, aimed at embedded applications. [62] Possibly Tolapai Spring, Arizona, USA. 2007 Tonga: CPU Pentium II Mobile processor, 250 nm. Probably the island ...
All models support: MMX L2 cache is off-die and runs at 50% CPU speed; The Pentium II OverDrive is a Deschutes Pentium II core packaged for Socket 8 operation. It comes with 512 KB of off-die full-speed L2 cache, which makes it very similar to the Pentium II Xeon.
Pentium Gold G7400E: 2 (4) 3.6 GHz — 2 × 1.25 MB 6 MB UHD 710 300–1350 MHz 46 W — LGA 1700 DMI 4.0 ×8 January 2022 SRL6R (H0) CM8071504653907 Low power: Pentium Gold G7400T: 2 (4) 3.1 GHz — 2 × 1.25 MB 6 MB UHD 710 300–1350 MHz 35 W — LGA 1700 DMI 4.0 ×8 January 2022 SRL65 (H0) CM8071504651504 Low power, embedded: Pentium Gold ...
P5 (Pentium) 5 200 800, 600, 350 nm 1995 P6 (Pentium Pro, Pentium II) 14 (17 with load & store/ retire) 450 500, 350, 250 nm 1997 P5 (Pentium MMX) 6 233 350 nm 1999 P6 (Pentium III) 12 (15 with load & store/retire) 1400 250, 180, 130 nm 2000 NetBurst (Pentium 4) (Willamette) 20 unified with branch prediction 2000 180 nm 2002 NetBurst (Pentium 4)
SSE was originally called Katmai New Instructions (KNI), Katmai being the code name for the first Pentium III core revision. During the Katmai project Intel sought to distinguish it from its earlier product line, particularly its flagship Pentium II. It was later renamed Internet Streaming SIMD Extensions (ISSE [2]), then SSE.
The default OperandSize and AddressSize to use for each instruction is given by the D bit of the segment descriptor of the current code segment - D=0 makes both 16-bit, D=1 makes both 32-bit. Additionally, they can be overridden on a per-instruction basis with two new instruction prefixes that were introduced in the 80386:
3.2 GHz – 3.73 GHz Socket 478 Socket T: 90 nm, 130 nm 92 W – 115 W 1 /w hyperthreading 800 MHz, 1066 MHz 8 KiB 512 KiB – 1 MiB 0 KiB – 2 MiB Pentium M: 7xx Banias Dothan: 2003–2008 800 MHz – 2.266 GHz Socket 479: 90 nm, 130 nm 5.5 W – 27 W 1 400 MHz, 533 MHz 32 KiB 1 MiB – 2 MiB N/A Pentium D/EE: 8xx 9xx Smithfield Presler