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Socket SP3 is a zero insertion force land grid array CPU socket designed by AMD supporting its Zen-, Zen 2- and Zen 3-based Epyc server processors, [1] [2] launched on June 20, 2017. [3] Because the socket is physically the same size as socket TR4 and socket sTRX4 , users can use CPU coolers not only designed for SP3, but also coolers designed ...
Socket 939: Troy 200 Socket 940: Athens 800 Denmark 100 2 1600–3200 1000 HT Socket 939: AMD64, NX Bit: Italy 200 1600–3200 Socket 940: AMD64, NX Bit, ccNUMA: Egypt 800 1600–3200 Santa Ana 1200 1800–3200 Socket AM2: DDR2: AMD64, NX Bit: Santa Rosa 2200 1800–3200 Socket F: 8200 2000–3000 130 Athlon 64 FX: Sledgehammer FX-51, FX-53 1 ...
Socket 1 Socket 2 Socket 3 0.6 – 1-micron 1 25 MHz – 50 MHz 8 KiB – 16 KiB N/A N/A Intel Pentium: N/A P5 P54C P54CTB P54CS 1993–1999 65 MHz – 250 MHz Socket 2 Socket 3 Socket 4 Socket 5 Socket 7: 350 nm – 800 nm Unknown 1 50 MHz – 66 MHz 16 KiB N/A N/A Intel Pentium MMX: N/A P55C Tillamook 1996–1999 120 MHz – 300 MHz Socket 7
It is possible to use Socket 7 processors in a Socket 5. An adapter is required, or if one is careful, a socket 7 can be pulled off its pins and put onto a socket 5 board, allowing the use of socket 7 processors. Socket 8: 1995 Intel Pentium Pro: PGA: 387 ? 60–66 MHz Slot 1: 1997 Intel Pentium II Intel Pentium III: Desktop Slot: 242 ? 66 ...
Socket 8 processor package (387 pins; Dual SPGA) 5.5 million transistors; Family 6 model 1; 0.6 μm process technology. 16 KB L1 cache; 256 KB integrated L2 cache; 60 MHz system bus clock rate; Variants 150 MHz; 0.35 μm process technology, (two die, a 0.35 μm CPU with 0.6 μm L2 cache) 5.5 million transistors; 512 KB or 256 KB integrated L2 cache
To keep costs low on high-volume competitive products, the CPU core is usually bundled into a system-on-chip (SOC) integrated circuit. SOCs contain the processor core, cache and the processor's local data on-chip, along with clocking, timers, memory (SDRAM), peripheral (network, serial I/O), and bus (PCI, PCI-X, ROM/Flash bus, I2C) controllers.
Socket 3 was a series of CPU sockets for various x86 microprocessors. It was sometimes found alongside a secondary socket designed for a math coprocessor chip, such as the 487 [citation needed]. Socket 3 resulted from Intel's creation of lower voltage microprocessors. An upgrade to Socket 2, it rearranged the pin layout. Socket 3 is compatible ...
While the SP3 server socket does not require a chipset, instead utilizing a system-on-a-chip design, TR4 and its successor HEDT sockets require a chipset to unlock the features of the CPU. For TR4, the AMD X399 chipset was released, which allows a total of 64 PCIe 3.0 lanes for quad SLI / CrossFire configurations.