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2. List of IOMMU-supporting hardware - Wikipedia

   en.wikipedia.org/wiki/List_of_IOMMU-supporting...

   The first—and least powerful—Xeon to support VT-d was the E5502 launched Q1'09 with two cores at 1.86 GHz on a 45 nm process. [2] Many or most Xeons subsequent to this support VT-d. See Advanced Search: feature=VT-d and segment=server for the full list.

3. List of AMD chipsets - Wikipedia

   en.wikipedia.org/wiki/List_of_AMD_chipsets

   Hudson-D3 [N 2] ×4 Gen 2 +DP 6× 6 Gbit/s AHCI 1.2 4 + 10 + 2 10/100/1000: 7.8 [15] First native USB 3.0 controller [16] 100-CG2386 [15] A78 Bolton-D3 [N 2] 6× 6 Gbit/s AHCI 1.3 7.8 xHCI 1.0 218-0844014 A85X Hudson-D4 [N 2] 8× 6 Gbit/s AHCI 1.2 0,1,5,10 10/100/1000: USB 3.0 (xHCI 0.96) 218-0755117 A88X Bolton-D4 [N 2] ×4 Gen 2 8× 6 Gbit/s ...

4. NVM Express - Wikipedia

   en.wikipedia.org/wiki/NVM_Express

   NVM Express over Fabrics (NVMe-oF) is the concept of using a transport protocol over a network to connect remote NVMe devices, contrary to regular NVMe where physical NVMe devices are connected to a PCIe bus either directly or over a PCIe switch to a PCIe bus.

5. M.2 - Wikipedia

   en.wikipedia.org/wiki/M.2

   The M.2 standard allows module widths of 12, 16, 22 and 30 mm, and lengths of 16, 26, 30, 38, 42, 60, 80 and 110 mm. Initial line-up of the commercially available M.2 expansion cards is 22 mm wide, with varying lengths of 30, 42, 60, 80 and 110 mm. [3] [5] [14] [18] The codes for the M.2 module sizes contain both the width and length of a ...

6. Direct Media Interface - Wikipedia

   en.wikipedia.org/wiki/Direct_Media_Interface

   DMI 1.0, introduced in 2004 with a data transfer rate of 1 GB/s with a ×4 link. DMI 2.0 , introduced in 2011, doubles the data transfer rate to 2 GB/s with a ×4 link. It is used to link an Intel CPU with the Intel Platform Controller Hub (PCH), which supersedes the historic implementation of a separate northbridge and southbridge.