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A minifloat in 1 byte (8 bit) with 1 sign bit, 4 exponent bits and 3 significand bits (in short, a 1.4.3 minifloat) is demonstrated here. The exponent bias is defined as 7 to center the values around 1 to match other IEEE 754 floats [ 3 ] [ 4 ] so (for most values) the actual multiplier for exponent x is 2 x −7 .
The advantage over 8-bit or 16-bit integers is that the increased dynamic range allows for more detail to be preserved in highlights and shadows for images, and avoids gamma correction. The advantage over 32-bit single-precision floating point is that it requires half the storage and bandwidth (at the expense of precision and range). [5]
This format is a shortened (16-bit) version of the 32-bit IEEE 754 single-precision floating-point format (binary32) with the intent of accelerating machine learning and near-sensor computing. [3] It preserves the approximate dynamic range of 32-bit floating-point numbers by retaining 8 exponent bits , but supports only an 8-bit precision ...
The 16-bit format is intended for the exchange or storage of small numbers (e.g., for graphics). The encoding scheme for these binary interchange formats is the same as that of IEEE 754-1985: a sign bit, followed by w exponent bits that describe the exponent offset by a bias , and p − 1 bits that describe the significand.
The Motorola 6888x math coprocessors and the Motorola 68040 and 68060 processors also support a 64-bit significand extended-precision format (similar to the Intel format, although padded to a 96-bit format with 16 unused bits inserted between the exponent and significand fields, and values with exponent zero and bit 63 one are normalized values ...
MBF numbers consist of an 8-bit base-2 exponent, a sign bit (positive mantissa: s = 0; negative mantissa: s = 1) and a 23-, [43] [8] 31-[8] or 55-bit [43] mantissa of the significand. There is always a 1-bit implied to the left of the explicit mantissa, and the radix point is located before this assumed bit .
[15] [16] [17] [19] As an 8-bit exponent was not wide enough for some operations desired for double-precision numbers, e.g. to store the product of two 32-bit numbers, [20] both Kahan's proposal and a counter-proposal by DEC therefore used 11 bits, like the time-tested 60-bit floating-point format of the CDC 6600 from 1965.
The IEEE Standard for Radix-Independent Floating-Point Arithmetic (IEEE 854), was the first Institute of Electrical and Electronics Engineers (IEEE) international standard for floating-point arithmetic with radices other than 2, including radix 10.