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Type 3 (CXL.io and CXL.mem) – allow the host to access and manage attached device memory, memory expansion boards and persistent memory. Devices provide host CPU with low-latency access to local DRAM or byte-addressable non-volatile storage. [38] Type 2 devices implement two memory coherence modes, managed by device driver.
A cache coherence protocol is used to maintain cache coherency. The two main types are snooping and directory-based protocols. Cache coherence is of particular relevance in multiprocessing systems, where each CPU may have its own local cache of a shared memory resource. Coherent caches: The value in all the caches' copies is the same.
The MESI protocol is an invalidate-based cache coherence protocol, and is one of the most common protocols that support write-back caches.It is also known as the Illinois protocol due to its development at the University of Illinois at Urbana-Champaign. [1]
– The cache is set M (D) if the "shared line" is off, otherwise is set O (SD). All the other copies are set S (V) Cache in E (R) or M (D) state (exclusiveness) – The write can take place locally without any other action. The state is set (or remains) M (D) Write Miss – Write Allocate – Read with Intent to Modified operation
Bus snooping or bus sniffing is a scheme by which a coherency controller (snooper) in a cache (a snoopy cache) monitors or snoops the bus transactions, and its goal is to maintain a cache coherency in distributed shared memory systems. This scheme was introduced by Ravishankar and Goodman in 1983, under the name "write-once" cache coherency. [1]
The MESIF protocol is a cache coherency and memory coherence protocol developed by Intel for cache coherent non-uniform memory architectures. [1] The protocol consists of five states, Modified (M), Exclusive (E), Shared (S), Invalid (I) and Forward (F).
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Coherent Accelerator Processor Interface (CAPI), is a high-speed processor expansion bus standard for use in large data center computers, initially designed to be layered on top of PCI Express, for directly connecting central processing units (CPUs) to external accelerators like graphics processing units (GPUs), ASICs, FPGAs or fast storage.