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This article gives a list of AMD microprocessors, sorted by generation and release year. If applicable and openly known, the designation(s) of each processor's core (versions) is (are) listed in parentheses. For an overview over concrete product, you then need to consult further articles, like e.g. list of AMD accelerated processing units.
AMD K6-2 – an improved K6 with the addition of the 3DNow! SIMD instructions. AMD K6-III Sharptooth – a further improved K6 with three levels of cache – 64 KB L1, 256 KB full-speed on-die L2, and a variable (up to 2 MB) L3. AMD K7 Athlon – microarchitecture of the AMD Athlon classic and Athlon XP microprocessors. Was a very advanced ...
AMD introduced TBM together with BMI1 in its Piledriver [27] line of processors; later AMD Jaguar and Zen-based processors do not support TBM. [28] No Intel processors (as of 2023) support TBM. The TBM instructions are all encoded using the XOP prefix. They are all available in 32-bit and 64-bit forms, selected with the XOP.W bit (0=32bit, 1 ...
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Move from general register to x86 debug register. [k] On Pentium and later processors, moves to the DR0-DR7 debug registers are serializing. MOV reg,TRx: 0F 24 /r [j] Move from x86 test register to general register. [n] MOV TRx,reg: 0F 26 /r [j] Move from general register to x86 test register. [n] ICEBP, INT01, INT1 [o] F1: In-circuit emulation ...
AMD was the first to introduce the instructions that now form Intel's BMI1 as part of its ABM (Advanced Bit Manipulation) instruction set, then later added support for Intel's new BMI2 instructions. AMD today advertises the availability of these features via Intel's BMI1 and BMI2 cpuflags and instructs programmers to target them accordingly. [2]
The x86 instruction set has several times been extended with SIMD (Single instruction, multiple data) instruction set extensions.These extensions, starting from the MMX instruction set extension introduced with Pentium MMX in 1997, typically define sets of wide registers and instructions that subdivide these registers into fixed-size lanes and perform a computation for each lane in parallel.