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2. List of Intel Xeon processors (Rocket Lake-based) - Wikipedia

   en.wikipedia.org/wiki/List_of_Intel_Xeon...

   "Intel Lists Xeon W-1300 CPUs: Rocket Lake for Workstations". Tom's Hardware This page was last edited on 15 May 2022, at ...

3. Lion Cove - Wikipedia

   en.wikipedia.org/wiki/Lion_Cove

   Lunar Lake's Lion Cove implementation contains a 2.5 MB L2 cache while the Lion Cove variant in Arrow Lake contains contains a 3 MB L2 cache. Lion Cove's larger L2 cache continues the trend of Intel increasing the size of the L2 cache for the last few generations of their P-cores such as Golden Cove , Raptor Cove and Redwood Cove .

4. Rocket Lake - Wikipedia

   en.wikipedia.org/wiki/Rocket_Lake

   Rocket Lake has up to eight cores, down from 10 cores for Comet Lake. It features Intel Xe graphics, and PCIe 4.0 support. [6] Only a single M.2 drive is supported in PCIe 4.0 mode, while all the rest are wired via PCIe 3.0. [7] Intel officially launched the Rocket Lake desktop family on March 16, 2021, with sales commencing on March 30. [8]

5. List of Intel CPU microarchitectures - Wikipedia

   en.wikipedia.org/wiki/List_of_Intel_CPU_micro...

   Alder Lake: hybrid processor, succeeds Rocket Lake and Tiger Lake, released on November 4, 2021. Gracemont is used in E-cores of Alder Lake processors. [21] Raptor Lake: a refresh of Alder Lake, released on October 20, 2022.

6. Sunny Cove (microarchitecture) - Wikipedia

   en.wikipedia.org/wiki/Sunny_Cove_(microarchitecture)

   Sunny Cove was designed by Intel Israel's processor design team in Haifa, Israel. [5] [6]Intel released details of Ice Lake and its microarchitecture, Sunny Cove, during Intel Architecture Day in December 2018, stating that the Sunny Cove cores would be focusing on single-thread performance, new instructions, and scalability improvements.

7. AVX-512 - Wikipedia

   en.wikipedia.org/wiki/AVX-512

   AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture (ISA) proposed by Intel in July 2013, and first implemented in the 2016 Intel Xeon Phi x200 (Knights Landing), [1] and then later in a number of AMD and other Intel CPUs (see list below).