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Some Xeon Phi processors support four-way hyper-threading, effectively quadrupling the number of threads. [1] Before the Coffee Lake architecture, most Xeon and all desktop and mobile Core i3 and i7 supported hyper-threading while only dual-core mobile i5's supported it.
List of Intel Xeon processors.
Based on Sandy Bridge microarchitecture.; All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), TXT, Intel VT-x, Intel EPT, Intel VT-d, Intel VT-c, [1] Intel x8 SDDC, [3] Hyper-threading (except E5-1603, E5-1607, E5-2603, E5-2609 and E5-4617), Turbo Boost (except E5-1603, E5-1607, E5-2603 ...
Sapphire Rapids Xeon server processors are scalable from single-socket configurations up to 8 socket configurations. [35] [36] Suffixes to denote: [37] +: Includes 1 of each of the four accelerators: DSA, IAA, QAT, DLB; H: Database and analytics workloads, supports 4S (Xeon Gold) and/or 8S (Xeon Platinum) configurations and includes all of the ...
All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, FMA3, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel EPT, Intel VT-d, Hyper-threading (except E5-1603 v3, E5-1607 v3, E5-2603 v3, E5-2609 v3, E5-2628 v3, E5-2663 v3, E5-2685 v3 and E5-4627 v3), Turbo Boost 2.0 (except E5-1603 v3, E5-1607 v3, E5-2603 v3 ...
Based on Penryn microarchitecture; Chip harvests from Yorkfield with half L2 cache disabled; All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, Enhanced Intel SpeedStep Technology (EIST), Enhanced Halt State (C1E), Intel 64, XD bit (an NX bit implementation), Intel VT-x
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Xeon E-2x 1 x 2 x 3: x 1 represents the generation. x 3 represents the number of cores. No suffix letter: without integrated GPU-G: with integrated GPU-M: BGA mobile processor-L: low power-E: embedded