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The NAND gate has the property of functional completeness, which it shares with the NOR gate. That is, any other logic function (AND, OR, etc.) can be implemented using only NAND gates. [2] An entire processor can be created using NAND gates alone. In TTL ICs using multiple-emitter transistors, it also requires fewer transistors than a NOR gate.
An XNOR gate is made by considering the disjunctive normal form + ¯ ¯, noting from de Morgan's law that a NAND gate is an inverted-input OR gate. This construction entails a propagation delay three times that of a single NAND gate and uses five gates.
A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs. This leads to an alternative set of symbols for basic gates that use the opposite core symbol (AND or OR) but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much ...
Schematic of basic two-input DTL NAND gate. R3, R4 and V− shift the positive output voltage of the input DL stage below the ground (to cut off the transistor at low input voltage). Diode–transistor logic (DTL) is a class of digital circuits that is the direct ancestor of transistor–transistor logic.
An SR latch constructed from cross-coupled NAND gates. The circuit shown below is a basic NAND latch. The inputs are also generally designated S and R for Set and Reset respectively. Because the NAND inputs must normally be logic 1 to avoid affecting the latching action, the inputs are considered to be inverted in this circuit (or active low).
The 3-input Fredkin gate is functionally complete reversible gate by itself – a sole sufficient operator. There are many other three-input universal logic gates, such as the Toffoli gate. In quantum computing, the Hadamard gate and the T gate are universal, albeit with a slightly more restrictive definition than that of functional completeness.
Due to the functional completeness property of the NAND and NOR gates, a full adder can also be implemented using nine NAND gates, [4] or nine NOR gates. Using only two types of gates is convenient if the circuit is being implemented using simple integrated circuit chips which contain only one gate type per chip.
As an example, consider the static logic implementation of a CMOS NAND gate: This circuit implements the logic function = ¯ If A and B are both high, the output will be pulled low. If either A or B are low, the output will be pulled high. At all times, the output is pulled either low or high.