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Socket 478, also known as mPGA478 or mPGA478B, is a 478-contact CPU socket used for Intel's Pentium 4 and Celeron series CPUs. Socket 478 was launched in August 2001 in advance of the Northwood core to compete with AMD 's 462-pin Socket A and their Athlon XP processors.
Some Socket 478 models supports loadline B (FMB1.0) with reduced TDP to 89 Watts (100.39 Watts peak) [19] Some LGA775 models supports Prescott FMB1 (775_VR_CONFIG_04A) with reduced TDP to 85 Watts (100.78 Watts peak)
Socket M for Intel Core, Core 2 and Celeron M 4xx and 5xx processors; and; Socket P for Core 2 processors. Even the Intel's CPU specifications seem to be not clear enough on the distinction and instead use the package/socket designations PGA478 or PPGA478 for more than 1 of the above sockets. [2] [3]
Intel Core 2 Duo T9600 CPU showing Socket P. The front-side bus (FSB) of CPUs that install in Socket P can run at 400, 533, 667, 800, or 1066 MT/s.By adapting the multiplier the frequency of the CPU can throttle up or down to save power, given that all Socket P CPUs support EIST, except for Celeron that do not support EIST.
Socket M is not pin-compatible with the older desktop Socket 478 (mPGA478B) or the newer mobile Socket P (mPGA478MN) by location of one pin; it is also incompatible with most [7] versions of the older mobile Socket 479. Pentium III-M processors designed for the first version of Socket 479 will physically fit into a Socket M, but are ...
Can accept some of Socket 478 CPU with an adapter Socket 495: 2000 Intel Celeron Intel Pentium III: Notebook PGA: 495 1.27 [3] 66–133 MHz Socket 603: 2001 Intel Xeon: Server PGA: 603 1.27 [4] 100–133 MHz 400–533 MT/s Socket 478/ Socket N: 2001 Intel Pentium 4 Intel Celeron Intel Pentium 4 EE Intel Pentium 4 M: Desktop PGA: 478 1.27 [5 ...
The Intel Pentium Dual-Core processors, E2140, E2160, E2180, E2200, and E2220 use the Allendale core, which includes 2 MB of native L2 cache, with half disabled leaving only 1 MB. This compares to the higher end Conroe core which features 4 MB L2 Cache natively.
Socket 8 processor package (387 pins; Dual SPGA) 5.5 million transistors; Family 6 model 1; 0.6 μm process technology. 16 KB L1 cache; 256 KB integrated L2 cache; 60 MHz system bus clock rate; Variants 150 MHz; 0.35 μm process technology, (two die, a 0.35 μm CPU with 0.6 μm L2 cache) 5.5 million transistors; 512 KB or 256 KB integrated L2 cache