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  2. Socket TR4 - Wikipedia

    en.wikipedia.org/wiki/Socket_TR4

    Socket TR4, also known as Socket SP3r2, is a zero insertion force land grid array (LGA) CPU socket designed by AMD supporting its first- and second-generation Zen-based Ryzen Threadripper desktop processors, [1] [2] launched on August 10, 2017 [3] for the high-end desktop and workstation platforms.

  3. List of AMD Ryzen processors - Wikipedia

    en.wikipedia.org/wiki/List_of_AMD_Ryzen_processors

    Common features of Ryzen 1000 HEDT CPUs: Socket: TR4. All the CPUs support DDR4-2666 in quad-channel mode. All the CPUs support 64 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset. No integrated graphics. L1 cache: 96 KB (32 KB data + 64 KB instruction) per core. L2 cache: 512 KB per core.

  4. Ryzen - Wikipedia

    en.wikipedia.org/wiki/Ryzen

    Socket AM4 for Ryzen and Socket TR4 for Ryzen Threadripper. [32] [33] Based on first generation Zen. Ryzen CPUs based on Summit Ridge architecture. Threadripper based on Whitehaven architecture. 4.8 billion transistors per 192 mm 2 [34] 8-core "Zeppelin" die [1] with one die being used for Ryzen and two for Ryzen Threadripper. Stepping: B1 [35 ...

  5. List of AMD chipsets - Wikipedia

    en.wikipedia.org/wiki/List_of_AMD_chipsets

    TR4 chipsets. Supports both 1st and 2nd generation AMD Ryzen Threadripper processors. [45] Model CPU ... TRX40 and WRX80 motherboards' CPU sockets use the same ...

  6. Table of AMD processors - Wikipedia

    en.wikipedia.org/wiki/Table_of_AMD_processors

    Socket TR4: Quad-channel DDR4: January 2019: Picasso Ryzen 3 (3300U, Pro 3300U, 3350U) ... List of AMD Ryzen microprocessors; List of AMD processors with 3D graphics;

  7. Threadripper - Wikipedia

    en.wikipedia.org/wiki/Threadripper

    Common features of Ryzen 1000 HEDT CPUs: Socket: TR4. All the CPUs support DDR4-2666 in quad-channel mode. All the CPUs support 64 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset. No integrated graphics. L1 cache: 96 KB (32 KB data + 64 KB instruction) per core. L2 cache: 512 KB per core.

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