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OCuLink (standing for "optical-copper link", since Cu is the chemical symbol for copper) is an extension for the "cable version of PCI Express". Version 1.0 of OCuLink, released in Oct 2015, supports up to 4 PCIe 3.0 lanes (3.9 GB/s) over copper cabling; a fiber optic version may appear in the future.
The PCI/104-Express specification establishes a standard to use the high-speed PCI Express bus in embedded applications. [1] It was developed by the PC/104 Consortium and adopted by member vote in March 2008. PCI Express was chosen because of its market adoption, performance, scalability, and growing silicon availability worldwide.
On August 2, 2022, the CXL Specification 3.0 was released, based on PCIe 6.0 physical interface and PAM-4 coding with double the bandwidth; new features include fabrics capabilities with multi-level switching and multiple device types per port, and enhanced coherency with peer-to-peer DMA and memory sharing.
The PCI-SIG is distinct from the similarly named and adjacently-focused PCI Industrial Computer Manufacturers Group. It has produced the PCI, PCI-X and PCI Express specifications. As of 2024, the board of directors of the PCI-SIG has representatives from: AMD, ARM, Dell EMC, IBM, Intel, Synopsys, Keysight, NVIDIA, and Qualcomm. The chairman and ...
USB4 has, from the start, referenced the PCI Express Specification Revision 4 and with USB4 Version 2.0 added references to PCI Express Specification Revision 5.0. PCIe tunneling has had a significant limitation in USB4 Version 1.0 and also Thunderbolt 3: PCIe Express has a variable maximum payload size, which applies end-to-end to a transmission.
The preferred interface for video cards then became Accelerated Graphics Port (AGP), a superset of PCI, before giving way to PCI Express. [5] The first version of PCI found in retail desktop computers was a 32-bit bus using a 33 MHz bus clock and 5 V signaling, although the PCI 1.0 standard provided for a 64-bit variant as well. [6]
Mobile PCI Express Module (MXM) is an interconnect standard for GPUs (MXM Graphics Modules) in laptops using PCI Express created by MXM-SIG. The goal was to create a non-proprietary, industry standard socket, so one could easily upgrade the graphics processor in a laptop, without having to buy a whole new system or relying on proprietary vendor upgrades.
The specification would be based on the PCI Express interface and NVM Express protocol. On 18 April 2017 the CompactFlash Association published the CFexpress 1.0 specification. [2] Version 1.0 will use the XQD form-factor (38.5 mm × 29.8 mm × 3.8 mm) with two PCIe 3.0 lanes for speeds up to 2 GB/s. NVMe 1.2 is used for low-latency access, low ...
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