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The 8051's instruction set is designed as a Harvard architecture with segregated memory (data and instructions); it can only execute code fetched from program memory and has no instructions to write to program memory.
Harvard architecture. The Harvard architecture is a computer architecture with separate storage [1] and signal pathways for instructions and data.It is often contrasted with the von Neumann architecture, where program instructions and data share the same memory and pathways.
SAB-C515-LN by Infineon is based on the 8051. The Infineon XC800 family is an 8-bit microcontroller family, first introduced in 2005, [1] with a dual cycle optimized 8051 "E-Warp" [2] [3] core. The XC800 family is divided into two categories, the A-Family for Automotive and the I-Family for Industrial and multi-market applications.
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However, on the 80386, with its paged memory management unit it is possible to protect individual memory pages against writing. [4] [5] Memory models are not limited to 16-bit programs. It is possible to use segmentation in 32-bit protected mode as well (resulting in 48-bit pointers) and there exist C language compilers which support that. [6]
Memory architecture also explains how binary digits are converted into electric signals and then stored in the memory cells. And also the structure of a memory cell. For example, dynamic memory is commonly used for primary data storage due to its fast access speed.
The DEC PDP-10, also 36-bit, had special instructions which allowed memory to be treated as a sequence of fixed-size bit fields or bytes of any size from 1 bit to 36 bits. A one-word sequence descriptor in memory, called a "byte pointer", held the current word address within the sequence, a bit position within a word, and the size of each byte.
Special function registers are in the upper area of addressable memory, from address 0x80 to 0xFF. This area of memory cannot be used for data or program storage, but is instead a series of memory-mapped ports and registers. All port input and output can therefore be performed by memory move operations on specified addresses in the SFR region.