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The VEX prefix replaces the most commonly used instruction prefix bytes and escape bytes. In many cases, the number of prefix bytes and escape bytes that are replaced is the same as the number of bytes in the VEX prefix, so that the total length of the VEX-encoded instruction is the same as the length of the legacy instruction code.
FMA4 instructions are encoded with the VEX prefix, on the form VEX.66.0F3A xx /r ib (no EVEX encodings are defined). The opcode byte xx uses its bottom bit to select floating-point format (0=FP32, 1=FP64) and the remaining bits to select one of the 10 fused-multiply-add operations to perform. For FMA4, operand ordering is controlled by the VEX ...
For all of the VEX-encoded instructions defined by BMI1 and BMI2, the operand size may be 32 or 64 bits, controlled by the VEX.W bit – none of these instructions are available in 16-bit variants. The VEX-encoded instructions are not available in Real Mode and Virtual-8086 mode - other than that, the bit manipulation instructions are available ...
The EVEX prefix retains fields introduced in the VEX prefix: Four bits R̅, X̅, B̅ and W from the VEX prefix, stored in inverted form. W expands the operand size to 64 bits or serves as an additional opcode, R expands reg, B expands r/m or reg, and X and B expand index and base in the SIB byte. Four bits named v̅, stored in inverted form.
The VEX prefix used by AVX and AVX2, while flexible, did not leave enough room for the features Intel wanted to add to AVX-512. This has led them to define a new prefix called EVEX. Compared to VEX, EVEX adds the following benefits: [7] Expanded register encoding allowing 32 512-bit registers.
160 bits (20 bytes) – maximum key length of the SHA-1, standard Tiger (hash function), and Tiger2 cryptographic message digest algorithms 2 8: 256 bits (32 bytes) – minimum key length for the recommended strong cryptographic message digests as of 2004 – size of an AVX2 vector register, present on newer x86-64 CPUs 2 9: 512 bits (64 bytes)
The XOP instructions have an opcode byte 8F (hexadecimal), but otherwise almost identical coding scheme as AVX with the 3-byte VEX prefix. Commentators [4] have seen this as evidence that Intel has not allowed AMD to use any part of the large VEX coding space. AMD has been forced to use different codes in order to avoid using any code ...
VEX coding is also used for instructions operating on the k0-k7 mask registers that were introduced with AVX-512. The alignment requirement of SIMD memory operands is relaxed. [5] Unlike their non-VEX coded counterparts, most VEX coded vector instructions no longer require their memory operands to be aligned to the vector size.