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2. 128-bit computing - Wikipedia

   en.wikipedia.org/wiki/128-bit_computing

   In computer architecture, 128-bit integers, memory addresses, or other data units are those that are 128 bits (16 octets) wide. Also, 128-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers, address buses, or data buses of that size. General home computing and gaming utility ...

3. Quadruple-precision floating-point format - Wikipedia

   en.wikipedia.org/wiki/Quadruple-precision...

   v. t. e. In computing, quadruple precision (or quad precision) is a binary floating-point –based computer number format that occupies 16 bytes (128 bits) with precision at least twice the 53-bit double precision. This 128-bit quadruple precision is designed not only for applications requiring results in higher than double precision, [1] but ...

4. RISC-V - Wikipedia

   en.wikipedia.org/wiki/RISC-V

   As a RISC architecture, the RISC-V ISA is a load–store architecture.Its floating-point instructions use IEEE 754 floating-point. Notable features of the RISC-V ISA include: instruction bit field locations chosen to simplify the use of multiplexers in a CPU, [2]: 17 a design that is architecturally neutral, [dubious – discuss] and a fixed location for the sign bit of immediate values to ...

5. Word (computer architecture) - Wikipedia

   en.wikipedia.org/wiki/Word_(computer_architecture)

   128. v. t. e. In computing, a word is the natural unit of data used by a particular processor design. A word is a fixed-sized datum handled as a unit by the instruction set or the hardware of the processor. The number of bits or digits [a] in a word (the word size, word width, or word length) is an important characteristic of any specific ...

6. IA-64 - Wikipedia

   en.wikipedia.org/wiki/IA-64

   128. IA-64 (Intel Itanium architecture) is the instruction set architecture (ISA) of the discontinued Itanium family of 64-bit Intel microprocessors. The basic ISA specification originated at Hewlett-Packard (HP), and was subsequently implemented by Intel in collaboration with HP. The first Itanium processor, codenamed Merced, was released in 2001.

7. SPARC - Wikipedia

   en.wikipedia.org/wiki/SPARC

   SPARC (Scalable Processor ARChitecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. [1][2] Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First developed in 1986 and released in 1987, [3][2] SPARC was one of the ...