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This is because DDR3 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer. With two transfers per cycle of a quadrupled clock signal, a 64-bit wide DDR3 module may achieve a transfer rate of up to 64 times the memory clock speed. With data being ...
For example, DDR3-2000 memory has a 1000 MHz clock frequency, which yields a 1 ns clock cycle. With this 1 ns clock, a CAS latency of 7 gives an absolute CAS latency of 7 ns. Faster DDR3-2666 memory (with a 1333 MHz clock, or 0.75 ns exactly; the 1333 is rounded) may have a larger CAS latency of 9, but at a clock frequency of 1333 MHz the ...
At higher clock rates, the useful CAS latency in clock cycles naturally increases. 10–15 ns is 2–3 cycles (CL2–3) of the 200 MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles.
JEDEC has set standards for the data rates of DDR SDRAM, divided into two parts. The first specification is for memory chips, and the second is for memory modules. The first retail PC motherboard using DDR SDRAM was released in August 2000. [10]
The naming convention for DDR, DDR2 and DDR3 modules specifies either a maximum speed (e.g., DDR2-800) or a maximum bandwidth (e.g., PC2-6400). The speed rating (800) is not the maximum clock speed, but twice that (because of the doubled data rate). The specified bandwidth (6400) is the maximum megabytes transferred per second using a 64-bit width.
With asynchronous DRAM, memory was accessed by a memory controller on the memory bus based on a set timing rather than a clock, and was separate from the system bus. [3] Synchronous DRAM , however, has a CAS latency that is dependent upon the clock rate.
Then, the base memory clock will operate at (Memory Divider) × (FSB) = 1 × 200 = 200 MHz and the effective memory clock would be 400 MHz since it is a DDR system ("DDR" stands for Double Data Rate; the effective memory clock speed is double the actual clock speed). The CPU will operate at 10 × 200 MHz = 2.0 GHz.
Memory clock I/O bus clock Transfer rate Theoretical bandwidth DDR-200, PC-1600 100 MHz 100 MHz 200 MT/s 1.6 GB/s DDR-400, PC-3200 200 MHz 200 MHz 400 MT/s 3.2 GB/s DDR2-800, PC2-6400 200 MHz 400 MHz 800 MT/s 6.4 GB/s DDR3-1600, PC3-12800 200 MHz 800 MHz 1600 MT/s 12.8 GB/s DDR4-2400, PC4-19200 300 MHz 1200 MHz 2400 MT/s 19.2 GB/s