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  2. Advanced eXtensible Interface - Wikipedia

    en.wikipedia.org/wiki/Advanced_eXtensible_Interface

    The Advanced eXtensible Interface (AXI) is an on-chip communication bus protocol and is part of the Advanced Microcontroller Bus Architecture specification (AMBA). [ 1 ] [ 2 ] AXI had been introduced in 2003 with the AMBA3 specification.

  3. Advanced Microcontroller Bus Architecture - Wikipedia

    en.wikipedia.org/wiki/Advanced_Microcontroller...

    In its second version, AMBA 2 in 1999, Arm added AMBA High-performance Bus (AHB) that is a single clock-edge protocol. In 2003, Arm introduced the third generation, AMBA 3, including Advanced eXtensible Interface (AXI) to reach even higher performance interconnect and the Advanced Trace Bus (ATB) as part of the CoreSight on-chip debug and trace ...

  4. Open Core Protocol - Wikipedia

    en.wikipedia.org/wiki/Open_Core_Protocol

    The Open Core Protocol (OCP) is a protocol for on-chip subsystem communications. It is an openly licensed, core-centric protocol and defines a bus-independent, configurable interface. OCP International Partnership produces OCP specifications. OCP data transfer models range from simple request-grant handshaking through pipelined request-response ...

  5. ARINC 429 - Wikipedia

    en.wikipedia.org/wiki/ARINC_429

    While it is common to illustrate serial protocol frames progressing in time from right to left, a reversed ordering is commonly practiced within the ARINC standard. Even though ARINC 429 word transmission begins with Bit 1 and ends with Bit 32, it is common to diagram [ 5 ] and describe [ 6 ] [ 7 ] ARINC 429 words in the order from Bit 32 to Bit 1.

  6. Master–slave (technology) - Wikipedia

    en.wikipedia.org/wiki/Master–slave_(technology)

    Computer bus protocols often use a master-slave relationship. For instance, a USB host manages access to the USB bus shared by any number of USB devices. A serial peripheral interface (SPI) bus typically has a single master controlling multiple slaves.

  7. Avionics Full-Duplex Switched Ethernet - Wikipedia

    en.wikipedia.org/wiki/Avionics_Full-Duplex...

    AFDX adopted concepts such as the token bucket from the telecom standards, Asynchronous Transfer Mode (ATM), to fix the shortcomings of IEEE 802.3 Ethernet. By adding key elements from ATM to those already found in Ethernet, and constraining the specification of various options, a highly reliable full-duplex deterministic network is created providing guaranteed bandwidth and quality of service ...

  8. ARM architecture family - Wikipedia

    en.wikipedia.org/wiki/ARM_architecture_family

    All modern ARM processors include hardware debugging facilities, allowing software debuggers to perform operations such as halting, stepping, and breakpointing of code starting from reset. These facilities are built using JTAG support, though some newer cores optionally support ARM's own two-wire "SWD" protocol. In ARM7TDMI cores, the "D ...

  9. Multidrop bus - Wikipedia

    en.wikipedia.org/wiki/Multidrop_bus

    The ccTalk multidrop bus protocol uses an 8 bit TTL-level asynchronous serial protocol.It uses address randomization to allow multiple similar devices on the bus (after randomisation the devices can be distinguished by their serial number). ccTalk was developed by CoinControls, but is used by multiple vendors.