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I/O devices are the pieces of hardware used by a human (or other system) to communicate with a computer. For instance, a keyboard or computer mouse is an input device for a computer, while monitors and printers are output devices .
It is designed to be paired with a second support chip known as a northbridge. As with any other southbridge, the ICH is used to connect and control peripheral devices. As CPU speeds increased data transmission between the CPU and support chipset, the support chipset eventually emerged as a bottleneck between the processor and the motherboard.
The vast majority of Intel server chips of the Xeon E3, Xeon E5, and Xeon E7 product lines support VT-d. The first—and least powerful—Xeon to support VT-d was the E5502 launched Q1'09 with two cores at 1.86 GHz on a 45 nm process. [2] Many or most Xeons subsequent to this support VT-d.
Thus, the use of vectored I/O (scatter-gather lists) can sometimes be avoided. Devices that do not support memory addresses long enough to address the entire physical memory can still address the entire memory through the IOMMU, avoiding overheads associated with copying buffers to and from the peripheral's addressable memory space.
The first use of channel I/O was with the IBM 709 [2] vacuum tube mainframe in 1957, whose Model 766 Data Synchronizer was the first channel controller. The 709's transistorized successor, the IBM 7090, [3] had two to eight 6-bit channels (the 7607) and a channel multiplexor (the 7606) which could control up to eight channels.
Memory-mapped I/O is preferred in IA-32 and x86-64 based architectures because the instructions that perform port-based I/O are limited to one register: EAX, AX, and AL are the only registers that data can be moved into or out of, and either a byte-sized immediate value in the instruction or a value in register DX determines which port is the source or destination port of the transfer.
Super I/O (sometimes Multi-IO) [1] is a class of I/O controller integrated circuits that began to be used on personal computer motherboards in the late 1980s, originally as add-in cards, later embedded on the motherboards. A super I/O chip combines interfaces for a variety of low-bandwidth devices. Now it is mostly merged with EC.
With appropriate support by the DASD hardware, PAV provides support for more than one I/O to a single device at a time. To maintain backward compatibility, operations are still serialized below the UCB level. But PAV allows the definition of additional UCBs to the same logical device, each using an additional alias address.