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Release date [130] Cores Clock L3 cache (total) Core config [a] Model Clock (GHz) Total Zen 4 Zen 4c Base Boost; Ryzen 9 7940HS: 8 (16) 8 (16) — 4.0 5.2 16 MB 1 × 8 780M 12 CU 2.8 Ryzen AI Up to 10 TOPS 20 35–54 W April 30, 2023 [b] 7940H [c] Ryzen 7 7840HS: 3.8 5.1 2.7 7840H [c] 7840U: 3.3 15–30 W May 3, 2023 [b] Ryzen 5 7640HS
Ryzen 5 7600 Ryzen 7 7700 Ryzen 9 7900 6/8/12 3700–3800 (5100–5400 boost) April 2023 Ryzen 7 7800X3D 8 4200 (5000 boost) 96 MB February 2023 Ryzen 9 7900X3D Ryzen 9 7950X3D 12/16 4200–4400 (5600–5700 boost) 96+32 MB March 2023 Phoenix Ryzen 7040 6/8 3800–4300 (5000–5200)
Release Date Part Number(s) ... Clock speed L2 cache FPU width [6] Hyper Transport Multi TDP Socket Release date ... Ryzen 9 5980HX [47] 8 (16) 3.3
These three models are the Ryzen 5 7600, Ryzen 7 7700, and Ryzen 9 7900, which feature a lower TDP of 65 W, and come bundled with stock coolers, unlike the X-suffix processors. [ 16 ] [ 17 ] The Ryzen 9 7900X3D and 7950X3D processors with 3D V-Cache were released on February 28, 2023, [ 18 ] followed by the Ryzen 7 7800X3D on April 6.
Clock rate L3 cache (total) TDP Chiplets Core config [i] Release date MSRP; Base Boost Ryzen Threadripper PRO 7995WX: 96 (192) 2.5 5.1 384 MB 350 W 12 × CCD
Common features of Ryzen AI 300 notebook APUs: Socket: BGA, FP8 package type. All models support DDR5-5600 or LPDDR5X-7500 in dual-channel mode. All models support 16 PCIe 4.0 lanes. Native USB 4 (40Gbps) Ports: 2; Native USB 3.2 Gen 2 (10Gbps) Ports: 2; iGPU uses the RDNA 3.5 microarchitecture. NPU uses the XDNA 2 AI Engine (Ryzen AI).
The Zen 5-based Ryzen 7 9800X3D has a 500 MHz increased base frequency over the Zen 4-based Ryzen 7 7800X3D and allows overclocking for the first time. [ 28 ] Ryzen AI 300 APUs, codenamed "Strix Point", features 24 MB of total L3 cache which is split into two separate cache arrays. 16 MB of dedicated L3 cache is shared the 4 Zen 5 cores and 8 ...
Common features of Ryzen 4000 notebook APUs: Socket: FP6. All the CPUs support DDR4-3200 or LPDDR4-4266 in dual-channel mode. L1 cache: 64 KB (32 KB data + 32 KB instruction) per core. L2 cache: 512 KB per core. All the CPUs support 16 PCIe 3.0 lanes. Includes integrated GCN 5th generation GPU. Fabrication process: TSMC 7FF.