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IRLZ24N Power MOSFET in a TO-220AB through-hole package. Pins from left to right are: gate (logic-level), drain, source. The top metal tab is the drain, same as pin 2. [1]A power MOSFET is a specific type of metal–oxide–semiconductor field-effect transistor (MOSFET) designed to handle significant power levels.
The threshold voltage, commonly abbreviated as V th or V GS(th), of a field-effect transistor (FET) is the minimum gate-to-source voltage (V GS) that is needed to create a conducting path between the source and drain terminals. It is an important scaling factor to maintain power efficiency.
The 2N7000 is housed in a TO92 package, with lead 1 connected as the source, lead 2 as the gate, and lead 3 as the drain. The BS170 has the source and drain leads interchanged. The 2N7002 variant is packaged in a TO-236 surface-mount package. The 2N7000 is an N-channel, enhancement-mode MOSFET used for low-power switching applications. [1]
The device consists of an active channel through which charge carriers, electrons or holes, flow from the source to the drain. Source and drain terminal conductors are connected to the semiconductor through ohmic contacts. The conductivity of the channel is a function of the potential applied across the gate and source terminals.
The source and drain (unlike the body) are highly doped as signified by a "+" sign after the type of doping. If the MOSFET is an n-channel or nMOS FET, then the source and drain are n+ regions and the body is a p region. If the MOSFET is a p-channel or pMOS FET, then the source and drain are p+ regions and the body is a n region. The source is ...
On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together.
where I DSS is the saturation current at zero gate–source voltage, i.e. the maximum current that can flow through the FET from drain to source at any (permissible) drain-to-source voltage (see, e. g., the I–V characteristics diagram above).
Top: source, bottom: drain, left: gate, right: bulk. Voltages that lead to channel formation are not shown. In field-effect transistors (FETs), depletion mode and enhancement mode are two major transistor types, corresponding to whether the transistor is in an on state or an off state at zero gate–source voltage.