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SHA-2: A family of two similar hash functions, with different block sizes, known as SHA-256 and SHA-512. They differ in the word size; SHA-256 uses 32-bit words where SHA-512 uses 64-bit words. There are also truncated versions of each standard, known as SHA-224, SHA-384, SHA-512/224 and SHA-512/256. These were also designed by the NSA.
The following tables compare general and technical information for a number of cryptographic hash functions. See the individual functions' articles for further information. This article is not all-inclusive or necessarily up-to-date. An overview of hash function security/cryptanalysis can be found at hash function security summary.
SHA-3 (Secure Hash Algorithm 3) is the latest [4] member of the Secure Hash Algorithm family of standards, released by NIST on August 5, 2015. [5] [6] [7] Although part of the same series of standards, SHA-3 is internally different from the MD5-like structure of SHA-1 and SHA-2.
Using SHA-1 as a hash function, the password is stretched into a 128-bit key 50,000 times before opening the document; as a result, the time required to crack it is vastly increased, similar to PBKDF2, scrypt or other KDFs. [citation needed] Office 2010 employed AES and a 128-bit key, but the number of SHA-1 conversions doubled to 100,000. [4]
Template: Comparison of SHA functions. ... Download QR code; Print/export ... SHA3-224 SHA3-256 SHA3-384 SHA3-512: 224 256 384 512: 1600
SHA-2 basically consists of two hash algorithms: SHA-256 and SHA-512. SHA-224 is a variant of SHA-256 with different starting values and truncated output. SHA-384 and the lesser-known SHA-512/224 and SHA-512/256 are all variants of SHA-512. SHA-512 is more secure than SHA-256 and is commonly faster than SHA-256 on 64-bit machines such as AMD64.
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Function Mix Inputs: V a, V b, V c, V d four 8-byte word entries from the work vector V x, y two 8-byte word entries from padded message m Output: V a, V b, V c, V d the modified versions of V a, V b, V c, V d V a ← V a + V b + x with input V d ← (V d xor V a) rotateright 32 V c ← V c + V d no input V b ← (V b xor V c) rotateright 24 V ...