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This 128-bit quadruple precision is designed not only for applications requiring results in higher than double precision, [1] but also, as a primary function, to allow the computation of double precision results more reliably and accurately by minimising overflow and round-off errors in intermediate calculations and scratch variables.
The register width of a processor determines the range of values that can be represented in its registers. Though the vast majority of computers can perform multiple-precision arithmetic on operands in memory, allowing numbers to be arbitrarily long and overflow to be avoided, the register width limits the sizes of numbers that can be operated on (e.g., added or subtracted) using a single ...
Arbitrary-precision arithmetic can also be used to avoid overflow, which is an inherent limitation of fixed-precision arithmetic. Similar to an automobile's odometer display which may change from 99999 to 00000, a fixed-precision integer may exhibit wraparound if numbers grow too large to represent at the fixed level of precision.
The binary interchange formats have the "half precision" (16-bit storage format) and "quad precision" (128-bit format) added, together with generalized formulae for some wider formats; the basic formats have 32-bit, 64-bit, and 128-bit encodings. Three new decimal formats are described, matching the lengths of the 32–128-bit binary formats.
On 5 January 1975, the 12-bit field that had been used for dates in the TOPS-10 operating system for DEC PDP-10 computers overflowed, in a bug known as "DATE75". The field value was calculated by taking the number of years since 1964, multiplying by 12, adding the number of months since January, multiplying by 31, and adding the number of days since the start of the month; putting 2 12 − 1 ...
The DEC VAX supported operations on 128-bit integer ('O' or octaword) and 128-bit floating-point ('H-float' or HFLOAT) datatypes. Support for such operations was an upgrade option rather than being a standard feature. Since the VAX's registers were 32 bits wide, a 128-bit operation used four consecutive registers or four longwords in memory.
The existing 64- and 128-bit formats follow this rule, but the 16- and 32-bit formats have more exponent bits (5 and 8 respectively) than this formula would provide (3 and 7 respectively). As with IEEE 754-1985, the biased-exponent field is filled with all 1 bits to indicate either infinity (trailing significand field = 0) or a NaN (trailing ...
The Motorola 6888x math coprocessors and the Motorola 68040 and 68060 processors also support a 64-bit significand extended-precision format (similar to the Intel format, although padded to a 96-bit format with 16 unused bits inserted between the exponent and significand fields, and values with exponent zero and bit 63 one are normalized values ...