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Epyc (stylized as EPYC) is a brand of multi-core x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced in June 2017, they are specifically targeted for the server and embedded system markets.
Common features: SP3 socket; Zen microarchitecture; GloFo 14 nm process; MCM with four System-on-a-chip (SOC) dies, two core complexes (CCX) per SOC die [1]; Eight-channel DDR4-2666 (the 7251 model is limited to DDR4-2400)
Model Cores ()Chiplets Core config [i] Clock rate Cache Socket Scaling TDP Release date Release price Base (GHz) Boost (GHz) L2 (per core) L3 (per CCX) Total 7232P
Genoa Epyc 9004 series (server) Genoa-X Epyc 9004X series (server) Bergamo Epyc 9704 series (server, Zen 4c cores) Siena Epyc 8004 series (server, Zen 4c cores) Zen 5 series CPUs and APUs (released 2024) Granite Ridge Ryzen 9000 series (desktop) Strix Point Ryzen AI 300 series (laptop) Turin Epyc 9005 series (server) Turin Dense Epyc (server ...
The Epyc server line of chips based on Zen 3 is named Milan and is the final generation of chips using the SP3 socket. [6] Epyc Milan was released on March 15, 2021. [65] Common features: SP3 socket; Zen 3 microarchitecture; TSMC 7 nm process for the compute and cache dies, GloFo 14 nm process for the I/O die
Bergamo (Epyc 9704 series) has up to 128 Zen 4c cores and is socket-compatible with Genoa. It was released in June 2023. [ 39 ] Another server product line that uses Zen 4c cores is Siena (Epyc 8004 series), which has up to 64 cores, uses a different smaller socket and is intended for use cases that favour smaller size, cost, power and thermal ...
AMD chipsets logo. This is an overview of chipsets sold under the AMD brand, manufactured before May 2004 by the company itself, before the adoption of open platform approach as well as chipsets manufactured by ATI Technologies after October 2006 as the completion of the ATI acquisition.
Socket FM1; CPU: K10 (also Husky or K10.5) cores with an upgraded Stars architecture, no L3 cache L1 cache: 64 KB Data per core and 64 KB Instruction cache per core; L2 cache: 512 KB on dual-core, 1 MB on tri- and quad-core models
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