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Some ECC-enabled boards and processors are able to support unbuffered (unregistered) ECC, but will also work with non-ECC memory; system firmware enables ECC functionality if ECC memory is installed. ECC may lower memory performance by around 2–3 percent on some systems, depending on the application and implementation, due to the additional ...
Two types of DIMMs: a 168-pin SDRAM module (top) and a 184-pin DDR SDRAM module (bottom). The SDRAM module has two notches (rectangular cuts or incisions) on the bottom edge, while the DDR1 SDRAM module has one. Also, each module has eight RAM chips, but the lower one has an unoccupied space for the ninth chip; this space is occupied in ECC DIMMs.
For example, 64 would indicate a 64-bit data width, as is found on non-ECC DIMMs common in SDR and DDR1–4 families of RAM. A memory of width of 72 would indicate an ECC module, with 8 extra bits in the data width for the error-correcting code syndrome. (The ECC syndrome allows single-bit errors to be corrected).
Modern DIMMs include a Serial Presence Detect (SPD) ROM chip that contains recommended memory timings for automatic configuration as well as XMP/EXPO profiles of faster timing information (and higher voltages) to allow for a performance boost via overclocking. The BIOS on a PC may allow the user to manually make timing adjustments in an effort ...
Normally, there is a performance penalty for using registered memory. Each read or write is buffered for one cycle between the memory bus and the DRAM, so the registered RAM can be thought of as running one clock cycle behind the equivalent unregistered DRAM.
Modern DIMMs can for example feature one rank (single rank), two ranks (dual rank), four ranks (quad rank), or eight ranks (octal rank). [ citation needed ] There is only a little difference between a dual rank UDIMM and two single-rank UDIMMs in the same memory channel, other than that the DRAMs reside on different PCBs .
Chips are made with a variety of data bus sizes (most commonly 4, 8 or 16 bits), but chips are generally assembled into 168-pin DIMMs that read or write 64 (non-ECC) or 72 bits at a time. Use of the data bus is intricate and thus requires a complex DRAM controller circuit.
An equivalent system from Sun Microsystems is called Extended ECC, while equivalent systems from HP are called Advanced ECC [3] and Chipspare. A similar system from Intel, called Lockstep memory, provides double-device data correction (DDDC) functionality. [4]