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S1, a 64-bit Wishbone compliant CPU core based on the OpenSPARC T1 design. It is a single UltraSPARC V9 core capable of 4-way SMT. Like the T1, the source code is licensed under the GPL. OpenSPARC T2, released in 2008, a 64-bit, 64-thread implementation conforming to the UltraSPARC Architecture 2007 and to SPARC Version 9 (Level 1). Source code ...
The SPARC T5 processor is used in Oracle's entry and mid-size SPARC T5-2, T5-4, and T5-8 servers. All servers use the same processor frequency, number of cores per chip and cache configuration. [12] The T5 processor includes a crossbar network that connects the 16 cores with the L2 caches to the shared L3 cache.
The chip is the first Sun/Oracle SPARC chip to use dynamic threading [3] and out-of-order execution. [4] It incorporates one floating point unit and one dedicated cryptographic unit per core. [ 2 ] The cores use the 64-bit SPARC Version 9 architecture running at frequencies between 2.85 GHz and 3.0 GHz, and are built in a 40 nm process with a ...
In the late 1990s, HAL Computer Systems, a subsidiary of Fujitsu, was designing a successor to the SPARC64 GP as the SPARC64 V. First announced at Microprocessor Forum 1999, the HAL SPARC64 V would have operated 1 GHz and had a wide superscalar organization with superspeculation, an L1 instruction trace cache, a small but very fast 8 KB L1 data cache, and separate L2 caches for instructions ...
Oracle Solaris is a proprietary Unix operating system offered by Oracle for SPARC and x86-64 based workstations and servers.Originally developed by Sun Microsystems as Solaris, it superseded the company's earlier SunOS in 1993 and became known for its scalability, especially on SPARC systems, and for originating many innovative features such as DTrace, ZFS and Time Slider.
On March 26, 2013, Oracle announced refreshed SPARC servers based on the new SPARC T5 microprocessor, which the company claims is "the world's fastest". [ 12 ] [ 13 ] [ 14 ] In the T5 range of servers, the single socket rackmount server design was deprecated, while a new eight-socket rackmount server was introduced.
OpenSPARC is an open-source hardware project, started in December 2005, for CPUs implementing the SPARC instruction architecture. The initial contribution to the project was Sun Microsystems' register-transfer level (RTL) Verilog code for a full 64-bit, 32-thread microprocessor, the UltraSPARC T1 processor.
The integer register file has 32 64-bit entries. As the SPARC ISA uses register windows, of which the UltraSPARC has eight, the actual number of registers is 144. The register file has seven read and three write ports.