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In computer architecture, a control bus is part of the system bus and is used by CPUs for communicating with other devices within the computer. While the address bus carries the information about the device with which the CPU is communicating and the data bus carries the actual data being processed, the control bus carries commands from the CPU and returns status signals from the devices.
A system bus is a single computer bus that connects the major components of a computer system, combining the functions of a data bus to carry information, an address bus to determine where it should be sent or read from, and a control bus to determine its operation. The technique was developed to reduce costs and improve modularity, and ...
The simplest system bus has completely separate input data lines, output data lines, and address lines. To reduce cost, most microcomputers have a bidirectional data bus, re-using the same wires for input and output at different times. [20] Some processors use a dedicated wire for each bit of the address bus, data bus, and the control bus.
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This bus: provides fully synchronous movement of GPR data between CPU and slave logic; functions as a synchronous, nonmultiplexed bus; has separate buses to read and to write data; consists of a single-master, multiple-slave bus; includes a 10-bit address bus; features 32-bit data buses; uses two-cycle minimum Read/Write cycles
For example, in a computer, address information is transmitted synchronously—the address bits over the address bus, and the read or write strobes of the control bus. Single-wire synchronous signalling. A logical one is indicated when there are two transitions in the same time frame as a zero.
Bus (computing), a communication system that transfers data between different components in a computer or between different computers Memory bus, a bus between the computer and the memory; PCI bus, a bus between motherboard and peripherals that uses the Peripheral Component Interconnect standard
The bus is completely asynchronous, allowing a mixture of fast and slow devices. It allows the overlapping of arbitration (selection of the next bus master) while the current bus master is still performing data transfers. The 18 address lines allow the addressing of a maximum of 256 KB.