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The number of bits needed for the precision and range desired must be chosen to store the fractional and integer parts of a number. For instance, using a 32-bit format, 16 bits may be used for the integer and 16 for the fraction. The eight's bit is followed by the four's bit, then the two's bit, then the one's bit.
The full decimal significand is then obtained by concatenating the leading and trailing decimal digits. The 10-bit DPD to 3-digit BCD transcoding for the declets is given by the following table. b 9 … b 0 are the bits of the DPD, and d 2 … d 0 are the three BCD digits.
The otherwise binary Wang VS machine supported a 64-bit decimal floating-point format in 1977. [2] The Motorola 68881 supported a format with 17 digits of mantissa and 3 of exponent in 1984, with the floating-point support library for the Motorola 68040 processor providing a compatible 96-bit decimal floating-point storage format in 1990. [2]
If an IEEE 754 single-precision number is converted to a decimal string with at least 9 significant digits, and then converted back to single-precision representation, the final result must match the original number. [6] The sign bit determines the sign of the number, which is the sign of the significand as well. "1" stands for negative.
On a typical computer system, a double-precision (64-bit) binary floating-point number has a coefficient of 53 bits (including 1 implied bit), an exponent of 11 bits, and 1 sign bit. Since 2 10 = 1024, the complete range of the positive normal floating-point numbers in this format is from 2 −1022 ≈ 2 × 10 −308 to approximately 2 1024 ≈ ...
For other binary formats, the required number of decimal digits is [h] + ⌈ ⌉, where p is the number of significant bits in the binary format, e.g. 237 bits for binary256. When using a decimal floating-point format, the decimal representation will be preserved using:
Using the fact that 2 10 = 1024 is only slightly more than 10 3 = 1000, 3n-digit decimal numbers can be efficiently packed into 10n binary bits. However, the IEEE formats have significands of 3 n +1 digits, which would generally require 10 n +4 binary bits to represent.
The IEEE 754 floating-point standard defines the exponent field of a single-precision (32-bit) number as an 8-bit excess-127 field. The double-precision (64-bit) exponent field is an 11-bit excess-1023 field; see exponent bias. It also had use for binary-coded decimal numbers as excess-3.