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  2. List of Intel CPU microarchitectures - Wikipedia

    en.wikipedia.org/wiki/List_of_Intel_CPU_micro...

    Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions. P5 original Pentium microprocessors, first x86 processor with super-scalar architecture and branch prediction. P6

  3. Template:Intel processor roadmap - Wikipedia

    en.wikipedia.org/wiki/Template:Intel_processor...

    is the desktop/laptop processor codename ("x86 TICK") is a spacer column; is the (single-core) NetBurst processor name. It is reserved to insert the NetBurst microarchitecture only, and is used solely to add NetBurst development in parallel with P6 development. Columns 9–13 are not anticipated to require any further updating unless Intel adds ...

  4. List of Intel codenames - Wikipedia

    en.wikipedia.org/wiki/List_of_Intel_codenames

    Platform 1/2/4/8-socket server platform combining Skylake/Ice Lake server/workstation processor(s) with Lewisburg chipset(s). Reference unknown. 2016 Queens Bay Platform Embedded platform combining the Atom E600 series processors (Tunnel Creek) with the EG20T PCH (Topcliff). Reference unknown. 2009 Radio Springs Motherboard Intel D945PLRN ...

  5. List of Intel processors - Wikipedia

    en.wikipedia.org/wiki/List_of_Intel_processors

    Intel Haswell Core i7-4771 CPU, sitting atop its original packaging that contains an OEM fan-cooled heatsink. This generational list of Intel processors attempts to present all of Intel's processors from the 4-bit 4004 (1971) to the present high-end offerings. Concise technical data is given for each product.

  6. Raptor Lake - Wikipedia

    en.wikipedia.org/wiki/Raptor_Lake

    The HX processors only support: DDR5-4800 (DDR5-5600 for i7-13850HX and above), DDR4-3200. The processors are connected to PCHs using an OPIO 2.0 x8 interface, except for the HX series which uses a DMI 4.0 x8 interface. [29] Except for the HX series, the processor and PCH are packaged together on a multi-chip package.

  7. Ivy Bridge (microarchitecture) - Wikipedia

    en.wikipedia.org/wiki/Ivy_Bridge_(microarchitecture)

    Ivy Bridge is the codename for Intel's 22 nm microarchitecture used in the third generation of the Intel Core processors (Core i7, i5, i3). Ivy Bridge is a die shrink to 22 nm process based on FinFET ("3D") Tri-Gate transistors , from the former generation's 32 nm Sandy Bridge microarchitecture—also known as tick–tock model .

  8. Granite Rapids - Wikipedia

    en.wikipedia.org/wiki/Granite_Rapids

    Granite Rapids is the codename for 6th generation Xeon Scalable server processors designed by Intel, launched on 24 September 2024. [1] [2] Featuring up to 128 P-cores, Granite Rapids is designed for high performance computing applications. The platform equivalent Sierra Forest processors with up to 288 E-cores launched in June 2024 before ...

  9. Alder Lake - Wikipedia

    en.wikipedia.org/wiki/Alder_Lake

    [4] [5] [6] The 10ESF has a 10%-15% boost in performance over the 10SF used in the mobile Tiger Lake processors. Intel officially announced 12th Gen Intel Core CPUs on October 27, 2021, [7] mobile CPUs and non-K series desktop CPUs on January 4, 2022, [8] Alder Lake-P and -U series on February 23, 2022, [9] and Alder Lake-HX series on May 10 ...

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