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P5 (Pentium) 5 200 800, 600, 350 nm 1995 P6 (Pentium Pro, Pentium II) 14 (17 with load & store/ retire) 450 500, 350, 250 nm 1997 P5 (Pentium MMX) 6 233 350 nm 1999 P6 (Pentium III) 12 (15 with load & store/retire) 1400 250, 180, 130 nm 2000 NetBurst (Pentium 4) (Willamette) 20 unified with branch prediction 2000 180 nm 2002 NetBurst (Pentium 4)
Logo from 1993 The latest standard badge design used by Intel to promote the Pentium brand. The Intel Pentium brand was a line of mainstream x86-architecture microprocessors from Intel. Processors branded Pentium Processor with MMX Technology (and referred to as Pentium MMX for brevity) are also listed here. It was replaced by the Intel ...
Intel Pentium Pro: 52x P6: 1995–1998 150 MHz – 200 MHz Socket 8: 350 nm, 500 nm 29.2 W – 47 W 1 60 MHz, 66 MHz 16 KiB 256 KiB, 512 KiB, 1024 KiB N/A Pentium II: 52x Klamath Deschutes Tonga Dixon: 1997–1999 233 MHz – 450 MHz Slot 1 MMC-1 MMC-2 Mini-Cartridge: 250 nm, 350 nm 16.8 W – 38.2 W 1 66 MHz, 100 MHz 32KiB 256 KiB – 512 KiB N/A
In October 1996, the Pentium MMX [7] was introduced, complementing the same basic microarchitecture of the original Pentium with the MMX instruction set, larger caches, and some other enhancements. Intel discontinued the P5 Pentium processors (sold as a cheaper product since the release of the Pentium II in 1997) in early 2000 in favor of the ...
560 560E 560X 560Z CPU: Pentium 100, 120, 133MHz: Pentium 150, 166MHz: Pentium 200, 233MHz MMX: Pentium II Mobile 233, 300MHz : HDD: 2.1 GB: 2.1 GB: 2.1-4.0 GB: 4.0-6 ...
All models support: MMX L2 cache is off-die and runs at 50% CPU speed; The Pentium II OverDrive is a Deschutes Pentium II core packaged for Socket 8 operation. It comes with 512 KB of off-die full-speed L2 cache, which makes it very similar to the Pentium II Xeon.
Pentium II processor with MMX technology. MMX defines eight processor registers, named MM0 through MM7, and operations that operate on them.Each register is 64 bits wide and can be used to hold either 64-bit integers, or multiple smaller integers in a "packed" format: one instruction can then be applied to two 32-bit integers, four 16-bit integers, or eight 8-bit integers at once.
28 million transistors; All models support: MMX, SSE The 'B' suffix denotes a 133 MHz FSB when the same speed was also available with a 100 MHz FSB. The 'E' suffix denotes a processor with support for Intel's Advanced Transfer Cache [1] in Intel documentation; in reality it indicates a Coppermine core when the same speed was available as either Katmai or Coppermine.
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