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The Intel QuickPath Interconnect (QPI) [1] [2] is a scalable processor interconnect developed by Intel which replaced the front-side bus (FSB) in Xeon, Itanium, and certain desktop platforms starting in 2008. It increased the scalability and available bandwidth. Prior to the name's announcement, Intel referred to it as Common System Interface ...
Nehalem / n ə ˈ h eɪ l əm / [1] is the codename for Intel's 45 nm microarchitecture released in November 2008. [2] It was used in the first generation of the Intel Core i5 and i7 processors, and succeeds the older Core microarchitecture used on Core 2 processors . [ 3 ]
Westmere (formerly Nehalem-C) is the code name given to the 32 nm die shrink of Nehalem. While sharing the same CPU sockets , Westmere included Intel HD Graphics , while Nehalem did not. The first Westmere -based processors were launched on January 7, 2010, by Intel Corporation.
The Intel X58 (codenamed Tylersburg) is an Intel chip designed to connect Intel processors with Intel QuickPath Interconnect (QPI) interface to peripheral devices. Supported processors implement the Nehalem microarchitecture and therefore have an integrated memory controller (IMC), so the X58 does not have a memory interface.
The following is a partial list of Intel CPU microarchitectures. The list is incomplete, additional details can be found in Intel's tick–tock model, process–architecture–optimization model and Template:Intel processor roadmap.
The Intel Ultra Path Interconnect (UPI) [1] [2] is a scalable processor interconnect developed by Intel which replaced the Intel QuickPath Interconnect (QPI) in Xeon Skylake-SP platforms starting in 2017.
Bottom view of a Core i7-2600K. Sandy Bridge is the codename for Intel's 32 nm microarchitecture used in the second generation of the Intel Core processors (Core i7, i5, i3).The Sandy Bridge microarchitecture is the successor to Nehalem and Westmere microarchitecture.
For high-end Nehalem processors, the X58 IOH acts as a bridge from the QPI to PCI Express peripherals and DMI to the ICH10 southbridge. For mainstream and lower-end Nehalem processors, the integrated memory controller (IMC) is an entire northbridge (some even having GPUs), and the PCH (Platform Controller Hub) acts as a southbridge.