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Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It is a JEDEC standard (JESD79-2); first published in September 2003. [2] DDR2 succeeded the original DDR SDRAM specification, and was itself succeeded by DDR3 SDRAM in 2007.
The Joint Electron Device Engineering Council characterizes its standardization efforts as follows: [1] JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the ...
A standard developed jointly with the JEDEC was published in October 2012. [13] [14] Version 3.1, published in october of 2012, includes errata to the original ONFI 3.0 specification, adds LUN SET/GET Features commands, and implements additional data setup and hold values for NV-DDR2 interface.
The DDR3 JEDEC standard for VLP DIMM height is around 0.740 inches (18.8 mm). These will fit vertically in ATCA systems. Full-height 240-pin DDR2 and DDR3 DIMMs are all specified at a height of around 1.18 inches (30 mm) by standards set by JEDEC. These form factors include 240-pin DIMM, SO-DIMM, Mini-DIMM and Micro-DIMM. [16]
DDR SDRAM specification was finalized by JEDEC in June 2000 (JESD79). [9] JEDEC has set standards for the data rates of DDR SDRAM, divided into two parts. The first specification is for memory chips, and the second is for memory modules. The first retail PC motherboard using DDR SDRAM was released in August 2000. [10]
JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for DDR, DDR2 and DDR3 SDRAM. SDRAM is also available in registered varieties, for systems that require greater scalability such as servers and workstations.
The term rank was created and defined by JEDEC, the memory industry standards group. On a DDR, DDR2, or DDR3 memory module, each rank has a 64-bit-wide data bus (72 bits wide on DIMMs that support ECC). The number of physical DRAMs depends on their individual widths.
Stub Series Terminated Logic (SSTL) is a group of electrical standards for driving transmission lines commonly used with DRAM based DDR memory IC's and memory modules. SSTL is primarily designed for driving the DDR (double-data-rate) SDRAM modules used in computer memory; however, it is also used in other applications, notably some PCI Express PHYs and other high-speed devices.