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It then instructs the DMA hardware to begin the transfer. When the transfer is complete, the device interrupts the CPU. Scatter-gather or vectored I/O DMA allows the transfer of data to and from multiple memory areas in a single DMA transaction. It is equivalent to the chaining together of multiple simple DMA requests.
This DMA controller uses the UART's DMA mode signals that were defined for the 16550. The DMA controller requires the CPU to set up each transaction and poll a status register after the transaction is started to determine if the transaction is done. Each DMA transaction can transfer between 1 and 128 bytes between a memory buffer and the UART.
This kind of transfer is implemented as "single mode transfer" in the Intel 8237 DMA controller. In multiword transfer mode, once a transfer has begun it will continue until all words are transferred or the drive negates the DMA request line. This mode is implemented as "demand mode transfer" in the Intel 8237 DMA controller.
The Ultra DMA (Ultra Direct Memory Access, UDMA) modes are the fastest methods used to transfer data through the ATA hard disk interface, usually between a computer and an ATA device. UDMA succeeded Single / Multiword DMA as the interface of choice between ATA devices and the computer.
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DDR3 modules can transfer data at a rate of 800–2133 MT/s using both rising and falling edges of a 400–1066 MHz I/O clock. This is twice DDR2's data transfer rates (400–1066 MT/s using a 200–533 MHz I/O clock) and four times the rate of DDR (200–400 MT/s using a 100–200 MHz I/O clock).
RDMA supports zero-copy networking by enabling the network adapter to transfer data from the wire directly to application memory or from application memory directly to the wire, eliminating the need to copy data between application memory and the data buffers in the operating system.
DMA is the only formal and predictable method for external devices to access RAM. This term is less common in modern computer architecture (above 66-100 MHz), where the various external buses and controllers generally run at different rates, and CPU internal operations are no longer closely coupled to I/O bus operations.