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  2. Random-access memory - Wikipedia

    en.wikipedia.org/wiki/Random-access_memory

    The use of semiconductor RAM dates back to 1965 when IBM introduced the monolithic (single-chip) 16-bit SP95 SRAM chip for their System/360 Model 95 computer, and Toshiba used bipolar DRAM memory cells for its 180-bit Toscal BC-1411 electronic calculator, both based on bipolar transistors.

  3. Computer memory - Wikipedia

    en.wikipedia.org/wiki/Computer_memory

    Historical lowest retail price of computer memory and storage Electromechanical memory used in the IBM 602, an early punch multiplying calculator Detail of the back of a section of ENIAC, showing vacuum tubes Williams tube used as memory in the IAS computer c. 1951 8 GB microSDHC card on top of 8 bytes of magnetic-core memory (1 core is 1 bit.)

  4. Giga-updates per second - Wikipedia

    en.wikipedia.org/wiki/Giga-updates_per_second

    GUPS is a measurement of how frequently a computer can issue updates to randomly generated RAM locations. GUPS measurements stress the latency and especially bandwidth capabilities of a machine. The BSS Random Access benchmark was proposed by IBM Research (Bhatotia, Sabharwal and Saxena at ACM/IEEE HiPC 2010) for measuring random memory access ...

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  6. DRAM price fixing scandal - Wikipedia

    en.wikipedia.org/wiki/DRAM_price_fixing_scandal

    DRAM SO-DIMM. In 2002, the United States Department of Justice, under the Sherman Antitrust Act, began a probe into the activities of dynamic random-access memory (DRAM) manufacturers in response to claims by US computer makers, including Dell and Gateway, that inflated DRAM pricing was causing lost profits and hindering their effectiveness in the marketplace.

  7. High Bandwidth Memory - Wikipedia

    en.wikipedia.org/wiki/High_Bandwidth_Memory

    High Bandwidth Memory (HBM) is a computer memory interface for 3D-stacked synchronous dynamic random-access memory (SDRAM) initially from Samsung, AMD and SK Hynix.It is used in conjunction with high-performance graphics accelerators, network devices, high-performance datacenter AI ASICs, as on-package cache in CPUs [1] and on-package RAM in upcoming CPUs, and FPGAs and in some supercomputers ...

  8. Dynamic random-access memory - Wikipedia

    en.wikipedia.org/wiki/Dynamic_random-access_memory

    This is the time to open a row, settle the sense amplifiers, and deliver the selected column data to the output. This is also the minimum /RAS low time, which includes the time for the amplified data to be delivered back to recharge the cells. The time to read additional bits from an open page is much less, defined by the /CAS to /CAS cycle time.

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