Ads
related to: rank in ddr2 c sharpwalmart.com has been visited by 1M+ users in the past month
Search results
Results from the WOW.Com Content Network
The term rank was created and defined by JEDEC, the memory industry standards group. On a DDR, DDR2, or DDR3 memory module, each rank has a 64-bit-wide data bus (72 bits wide on DIMMs that support ECC). The number of physical DRAMs depends on their individual widths.
Ranks are sub-units of a memory module that share the same address and data buses and are selected by chip select (CS) in low-level addressing. For example, a memory module with 8 chips on each side, with each chip having an 8-bit-wide data bus, would have one rank for each side for a total of 2 ranks, if we define a rank to be 64 bits wide.
1GB 2Rx4 PC2-3200P-333-11-D2 is a 1 GB DDR2 Registered DIMM, with address/command parity function, using 2 ranks of x4 SDRAMs operational to PC2-3200 performance with CAS Latency = 3, tRCD = 3, tRP = 3, using JEDEC SPD revision 1.1, raw card reference design file D revision 2 used for the assembly.
Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It is a JEDEC standard (JESD79-2); first published in September 2003. [2] DDR2 succeeded the original DDR SDRAM specification, and was itself succeeded by DDR3 SDRAM in 2007.
72-pin SO-DIMM. There are numerous DIMM variants, employing different pin-counts: DIMM. 100-pin: printer SDRAM and printer ROM (e.g., PostScript); 168-pin: SDR SDRAM sometimes used for FPM/EDO DRAM in workstations or servers, may be 3.3 or 5 V
There is a common belief that number of module ranks equals number of sides. As above data shows, this is not true. One can also find 2-side/1-rank modules. One can even think of a 1-side/2-rank memory module having 16(18) chips on single side ×8 each, but it is unlikely such a module was ever produced.
Ads
related to: rank in ddr2 c sharpwalmart.com has been visited by 1M+ users in the past month