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A Harvard architecture computer can thus be faster for a given circuit complexity because instruction fetches and data access do not contend for a single memory pathway. Also, a Harvard architecture machine has distinct code and data address spaces: instruction address zero is not the same as data address zero.
By contrast, von Neumann and split-cache modified Harvard machines store both instructions and data in a single address space, so address "zero" refers to only one location and whether the binary pattern in that location is interpreted as an instruction or data is defined by how the program is written.
The AVR is a modified Harvard architecture machine, where program and data are stored in separate physical memory systems that appear in different address spaces, but having the ability to read data items from program memory using special instructions.
IO5 is a 5-bit I/O address covering the bit-addressable part of the I/O address space, i.e. the lower half (range: 0–31) IO6 is a 6-bit I/O address covering the full I/O address space (range: 0–63) D16 is a 16-bit data address covering 64 KiB; in parts with more than 64 KiB data space, the contents of the RAMPD segment register is prepended
Having separate address spaces for instruction and data memory is what (in my opinion) defines the Harvard architecture. Assuming that there is only one instruction memory address space (I can't think of a reason to have more than one), that still leaves the door open for more than one data address space.
The SHARC is a Harvard architecture word-addressed VLIW processor; it knows nothing of 8-bit or 16-bit values since each address is used to point to a whole 32-bit word, not just an octet. It is thus neither little-endian nor big-endian, though a compiler may use either convention if it implements 64-bit data and/or some way to pack multiple 8 ...
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In a Harvard architecture or modified Harvard architecture, a separate virtual address space or memory-access hardware may exist for instructions and data. This can lead to distinct TLBs for each access type, an instruction translation lookaside buffer (ITLB) and a data translation lookaside buffer (DTLB). Various benefits have been ...