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Northbridge or host bridge for PowerPC CPU is an Integrated Circuit (IC) for interfacing PowerPC CPU with memory, and Southbridge IC. Some Northbridge also provide interface for Accelerated Graphics Ports (AGP) bus, Peripheral Component Interconnect (PCI), PCI-X, PCI Express, or Hypertransport bus. Specific Northbridge IC must be used for ...
The RAD5500 core is based on those of the Freescale Semiconductor e5500-based QorIQ system-on-chip.The RAD5510, RAD5515, RAD5545, RADSPEED-HB (host bridge), and RAD510 are five system on a chip processors implemented with RAD5500 cores produced with 45 nm SOI technology from the IBM Trusted Foundry.
A common example of a northbridge on a PowerPC platform is in Apple's older PowerPC-based computers like the iMac G5, which utilized an IBM CPC945 Northbridge chip. According to an Apple Developer note, The Power Mac G5's northbridge chip connected to a "Mid Bridge", which then connected to a south bridge. [9]
The ISA evolved into the PowerPC instruction set architecture and was deprecated in 1998 when IBM introduced the POWER3 processor that was mainly a 32/64-bit PowerPC processor but included the IBM POWER architecture for backwards compatibility. The original IBM POWER architecture was then abandoned.
The PowerPC 5000 family is a series of PowerPC and Power ISA microprocessors from Freescale (previously Motorola) and STMicroelectronics designed for automotive and industrial microcontroller and system on a chip (SoC) use. The MPC5000 family consists of two lines (51xx/52xx and 55xx/56xx) that really don't share a common heritage.
After two years of development, the resulting PowerPC ISA was introduced in 1993. A modified version of the RSC architecture, PowerPC added single-precision floating point instructions and general register-to-register multiply and divide instructions, and removed some POWER features. It also added a 64-bit version of the ISA and support for SMP.
Power ISA is an evolution of the PowerPC ISA, created by the mergers of the core PowerPC ISA and the optional Book E for embedded applications. The merger of these two components in 2006 was led by Power.org founders IBM and Freescale Semiconductor. Prior to version 3.0, the ISA is divided into several categories.
DMI 1.0, introduced in 2004 with a data transfer rate of 1 GB/s with a ×4 link.. DMI 2.0, introduced in 2011, doubles the data transfer rate to 2 GB/s with a ×4 link.It is used to link an Intel CPU with the Intel Platform Controller Hub (PCH), which supersedes the historic implementation of a separate northbridge and southbridge.