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The 65 nm process is an advanced lithographic node used in volume CMOS semiconductor fabrication. Printed linewidths (i.e. transistor gate lengths) can reach as low as 25 nm on a nominally 65 nm process, while the pitch between two lines may be greater than 130 nm.
Yonah is the code name of Intel's first generation 65 nm process CPU cores, based on cores of the earlier Banias (130 nm) / Dothan (90 nm) Pentium M microarchitecture.Yonah CPU cores were used within Intel's Core Solo and Core Duo mobile microprocessor products.
The technology used a 32 nm SOI process, two CPU cores per module, and up to four modules, ranging from a quad-core design costing approximately US$130 to a $280 eight-core design. Ambarella Inc. announced the availability of the A7L system-on-a-chip circuit for digital still cameras, providing 1080p60 high-definition video capabilities in ...
Tigerton dual-cores and all quad-core processors except - are multi-chip modules combining two dies. For the 65 nm processors, the same product code can be shared by processors with different dies, but the specific information about which one is used can be derived from the stepping.
65 nm, 90 nm 95 W – 130 W 2 533 MHz, 800 MHz, 1066 MHz 16 KiB per core 2×1 MiB – 2×2 MiB N/A Pentium Dual-Core: E2xxx E3xxx E5xxx T2xxx T3xxx Allendale Penryn Wolfdale Yonah: 2006–2009 1.6 GHz – 2.93 GHz Socket 775 Socket M Socket P Socket T: 45 nm, 65 nm 10 W – 65 W 2 533 MHz, 667 MHz, 800 MHz, 1066 MHz 64 KiB per core 1 MiB – 2 MiB
To keep costs low on high-volume competitive products, the CPU core is usually bundled into a system-on-chip (SOC) integrated circuit. SOCs contain the processor core, cache and the processor's local data on-chip, along with clocking, timers, memory (SDRAM), peripheral (network, serial I/O), and bus (PCI, PCI-X, ROM/Flash bus, I2C) controllers.
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Clock speed from 1 GHz to 2 GHz; Bus speed of 533 MHz or 800 MHz (1066 MHz for Nano x2) 64 KB data and 64 KB instructions L1 cache and 1 MB L2 cache per core. [16] 65 nm manufacturing process (40 nm for Nano x2) Superscalar out-of-order instruction execution; Support for MMX, SSE, SSE2, SSE3, SSSE3, and SSE4 instruction set