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  2. Stepping level - Wikipedia

    en.wikipedia.org/wiki/Stepping_level

    For example, executing CPUID instruction with the EAX register set to '1' on x86 CPUs will result in values being placed in other registers that show the CPU's stepping level. Stepping identifiers commonly comprise a letter followed by a number, for example B2. Usually, the letter indicates the revision level of a CPU's base layers and the ...

  3. Stepping (debugging) - Wikipedia

    en.wikipedia.org/wiki/Stepping_(debugging)

    Instruction stepping or single cycle originally referred to the technique of stopping the processor clock and manually advancing it one cycle at a time. For this to be possible, three things are required: A control that allows the clock to be stopped (e.g. a "Stop" button).

  4. Trap flag - Wikipedia

    en.wikipedia.org/wiki/Trap_flag

    The contents of registers and memory locations can be examined; if they are correct, the system can be told to go on and execute the next instruction. The Intel 8086 trap flag and type-1 interrupt response make it quite easy to implement a single-step feature in an 8086-based system. If the trap flag is set, the 8086 will automatically do a ...

  5. CPUID - Wikipedia

    en.wikipedia.org/wiki/CPUID

    Stepping ID is a product revision number assigned due to fixed errata or other changes. The actual processor model is derived from the Model, Extended Model ID and Family ID fields. If the Family ID field is either 6 or 15, the model is equal to the sum of the Extended Model ID field shifted left by 4 bits and the Model field.

  6. x86 debug register - Wikipedia

    en.wikipedia.org/wiki/X86_debug_register

    Single-Step execution (enabled by EFLAGS.TF) [d] 15: BT: Task Switch breakpoint. [d] Occurs when a task switch is done with a TSS that has the T (debug trap flag) bit set. 16: RTM (Processors with Intel TSX only) Cleared to 0 by the processor for debug exceptions inside RTM transactions, [f] set to 1 for all debug exceptions outside transactions.

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  8. Intel microcode - Wikipedia

    en.wikipedia.org/wiki/Intel_Microcode

    Final determination and validation of whether an update can be applied to a processor is performed during decryption via the processor. [18] Each microcode update is specific to a particular CPU revision, and is designed to be rejected by CPUs with a different stepping level. Microcode updates are encrypted to prevent tampering and to enable ...

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