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The frequency at which a processor (CPU) operates is determined by applying a clock multiplier to the front-side bus (FSB) speed in some cases. For example, a processor running at 3200 MHz might be using a 400 MHz FSB.
Toggle Mobile CPU subsection. 2.1 Mobile K6 (Model 7, K6, 250 nm) ... FSB 1 Multiplier Voltage TDP Socket Release Date Order Part Number(s) Release price K6 166:
Processor FSB supported Memory type supported High-speed interfaces provided Preferred IOCH 860 [12] Colusa 400 MT/s Two channels of ECC RDRAM at 800 or 600 MT/s, up to 3.2 GB/s AGP 4× port and three hub interfaces for two 533 MB/s PCI buses and a 266 MB/s bus to ICH2 ICH2 E7205 Granite Bay 400 or 533 MT/s
Note 1: Athlons use a double data rate (DDR) front-side bus, (EV-6) meaning that the actual data transfer rate of the bus is twice its physical clock rate. The FSB's true data rate, 200 or 266 MT/s, is used in the tables, and the physical clock rates are 100 and 133 MHz, respectively.
In PCs, the CPU's external address and data buses connect the CPU to the rest of the system via the "northbridge". Nearly every desktop CPU produced since the introduction of the 486DX2 in 1992 has employed a clock multiplier to run its internal logic at a higher frequency than its external bus, but still remain synchronous with it. This ...
Model number Frequency L2 cache HT Multi [a] Voltage TDP Socket Release date Order part number Turion 64 ML-28: 1600 MHz: 512 KB: 800 MHz: 8x: 1.35: 35 W: Socket 754: June 22, 2005
The 'B' suffix denotes a 133 MHz FSB when the same speed was also available with a 100 MHz FSB. The 'E' suffix denotes a processor with support for Intel's Advanced Transfer Cache [1] in Intel documentation; in reality it indicates a Coppermine core when the same speed was available as either Katmai or Coppermine. The 'E' suffix was not used on ...
Marketing name Model number Clock speed Turbo Speed L1 cache L2 cache FSB speed TDP Idle power Socket Cores Release date Nano X2 E: L4050: 1.4 GHz: 1.4 GHz: 64+64 KB per core