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This article gives a list of AMD microprocessors, sorted by generation and release year.If applicable and openly known, the designation(s) of each processor's core (versions) is (are) listed in parentheses.
Socket AM5: Dual-channel DDR5: MMX ... List of AMD processors with 3D graphics; List of Intel microprocessors; List of Intel CPU microarchitectures; Comparison of ...
Common features of Ryzen 9000 desktop CPUs: Socket: AM5. All the CPUs support DDR5-5600 in dual-channel mode. All the CPUs support 28 PCIe 5.0 lanes. 4 of the lanes are reserved as link to the chipset. Includes integrated RDNA2 GPU with 2 CUs and base, boost clock speeds of 0.4 GHz, 2.2 GHz. L1 cache: 80 KB (48 KB data + 32 KB instruction) per ...
AMD Zen 3+ Family 19h – 2022 revision of Zen 3 used in Ryzen 6000 mobile processors using a 6 nm process. AMD Zen 4 Family 19h – fourth generation Zen architecture, in 5 nm process. [5] Used in Ryzen 7000 consumer processors on the new AM5 platform with DDR5 and PCIe 5.0 support. Adds support for AVX-512 instruction set.
Socket AM5 (LGA 1718) is a zero insertion force flip-chip land grid array (LGA) [1] CPU socket designed by AMD that is used for AMD Ryzen microprocessors starting with the Zen 4 microarchitecture. [ 2 ] [ 3 ] AM5 was launched in September 2022 and is the successor to AM4 .
Common features of Ryzen 9000 desktop CPUs: Socket: AM5. All the CPUs support DDR5-5600 in dual-channel mode. All the CPUs support 28 PCIe 5.0 lanes. 4 of the lanes are reserved as link to the chipset. Includes integrated RDNA2 GPU with 2 CUs and base, boost clock speeds of 0.4 GHz, 2.2 GHz. L1 cache: 80 KB (48 KB data + 32 KB instruction) per ...
Opteron is a central processing unit (CPU) family within the AMD64 line. Designed by Advanced Micro Devices (AMD) for the server market, Opteron competed with Intel's Xeon. The Opteron family is succeeded by the Zen-based Epyc, and Ryzen Threadripper and Threadripper Pro series.
Common features of Ryzen 7000 desktop CPUs: Socket: AM5. All the CPUs support DDR5-5200 in dual-channel mode. L1 cache: 64 KB (32 KB data + 32 KB instruction) per core. L2 cache: 1 MB per core. All the CPUs support 28 PCIe 5.0 lanes. 4 of the lanes are reserved as link to the chipset.
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