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One of the major improvements the PCI Local Bus had over other I/O architectures was its configuration mechanism. In addition to the normal memory-mapped and I/O port spaces, each device function on the bus has a configuration space, which is 256 bytes long, addressable by knowing the eight-bit PCI bus, five-bit device, and three-bit function numbers for the device (commonly referred to as the ...
Burst reads (using linear incrementing) are permitted in PCI configuration space. Unlike I/O space, standard PCI configuration registers are defined so that reads never disturb the state of the device. It is possible for a device to have configuration space registers beyond the standard 64 bytes which have read side effects, but this is rare. [31]
The distinction can be arbitrary between a computer bus, often closer in space, and larger telecommunications networks. Many device interfaces or protocols (e.g., SATA, USB, SAS , PCIe ) are used both inside many-device boxes, such as a PC, and one-device-boxes, such as a hard drive enclosure .
PCI Express Mini Card (also known as Mini PCI Express, Mini PCIe, Mini PCI-E, mPCIe, and PEM), based on PCI Express, is a replacement for the Mini PCI form factor. It is developed by the PCI-SIG . The host device supports both PCI Express and USB 2.0 connectivity, and each card may use either standard.
Exposed configuration and monitoring operations include power management, control of Address Resolution Protocol (ARP) offloading, configuration of the out-of-band management traffic (which can be separated from the Ethernet traffic visible to the operating system by using RMCP ports filtering, a separate MAC address, or through VLAN tagging ...
Memory-mapped I/O is preferred in IA-32 and x86-64 based architectures because the instructions that perform port-based I/O are limited to one register: EAX, AX, and AL are the only registers that data can be moved into or out of, and either a byte-sized immediate value in the instruction or a value in register DX determines which port is the source or destination port of the transfer.
The PCI-X standard was developed jointly by IBM, HP, and Compaq and submitted for approval in 1998. It was an effort to codify proprietary server extensions to the PCI local bus to address several shortcomings in PCI, and increase performance of high bandwidth devices, such as Gigabit Ethernet, Fibre Channel, and Ultra3 SCSI cards, and allow processors to be interconnected in clusters.
A peripheral using the PCI-SIG PCIe Address Translation Services (ATS) Page Request Interface (PRI) extension can detect and signal the need for memory manager services. For system architectures in which port I/O is a distinct address space from the memory address space, an IOMMU is not used when the CPU communicates with devices via I/O ports ...