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In computer architecture, 36-bit integers, memory addresses, or other data units are those that are 36 bits (six six-bit characters) wide. Also, 36-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers, address buses, or data buses of that size. 36-bit computers were popular in the early mainframe computer era from the 1950s ...
In computing, PSE-36 (36-bit Page Size Extension) [1] refers to a feature of x86 processors that extends the physical memory addressing capabilities from 32 bits to 36 bits, allowing addressing to up to 64 GB of memory. [2]
For example, an 8-bit-byte-addressable machine with a 20-bit address bus (e.g. Intel 8086) can address 2 20 (1,048,576) memory locations, or one MiB of memory, while a 32-bit bus (e.g. Intel 80386) addresses 2 32 (4,294,967,296) locations, or a 4 GiB address space. In contrast, a 36-bit word-addressable machine with an 18-bit address bus ...
The size of the "byte offset" from the address being translated is still 12 bits, so total physical address size increases from 32 bits to 36 bits (i.e. from 20+12 to 24+12). This increased the physical memory that is theoretically addressable by the CPU from 4 GB to 64 GB.
Most 8-bit general-purpose microprocessors have 16-bit address spaces and generate 16 address lines. Examples include the Intel 8080, Intel 8085, Zilog Z80, Motorola 6800, Microchip PIC18, and many others. These processors have 8-bit CPUs with 8-bit data and 16-bit addressing. The memory on these CPUs is addressable at the byte level.
A workaround first developed in the Pentium Pro, known as Physical Address Extension (PAE), allows certain 32-bit operating systems to access up to 36-bit memory addresses, even though individual programs are still limited to operating within 32 bits of address space. Provided there is enough memory installed, each program can have its own four ...
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The only major change to the architecture is the addition of multi-section extended addressing in the KL-10; extended addressing, which changes the process of generating the effective address of an instruction, is briefly discussed at the end. Generally, the system has 36-bit words and instructions, and 18-bit addresses.