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  2. List of Intel CPU microarchitectures - Wikipedia

    en.wikipedia.org/wiki/List_of_Intel_CPU_micro...

    Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions. P5 original Pentium microprocessors, first x86 processor with super-scalar architecture and branch prediction. P6

  3. IA-64 - Wikipedia

    en.wikipedia.org/wiki/IA-64

    IA-64 (Intel Itanium architecture) is the instruction set architecture (ISA) of the discontinued Itanium family of 64-bit Intel microprocessors. The basic ISA specification originated at Hewlett-Packard (HP), and was subsequently implemented by Intel in collaboration with HP. The first Itanium processor, codenamed Merced, was released in 2001.

  4. Model-specific register - Wikipedia

    en.wikipedia.org/wiki/Model-specific_register

    The Intel Model-Specific Registers (MSRs) are described in-depth in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4; the link to the Intel reference manuals (PDFs) download page (which includes Vol 4):

  5. Machine Check Architecture - Wikipedia

    en.wikipedia.org/wiki/Machine_check_architecture

    In computing, Machine Check Architecture (MCA) is an Intel and AMD mechanism in which the CPU reports hardware errors to the operating system.. Intel's P6 and Pentium 4 family processors, AMD's K7 and K8 family processors, as well as the Itanium architecture implement a machine check architecture that provides a mechanism for detecting and reporting hardware (machine) errors, such as: system ...

  6. SSSE3 - Wikipedia

    en.wikipedia.org/wiki/SSSE3

    SSSE3 contains 16 new discrete instructions. Each instruction can act on 64-bit MMX or 128-bit XMM registers. Therefore, Intel's materials refer to 32 new instructions. They include: [1] Twelve instructions that perform horizontal addition or subtraction operations. Six instructions that evaluate absolute values.

  7. Intel Fortran Compiler - Wikipedia

    en.wikipedia.org/wiki/Intel_Fortran_Compiler

    The compilers generate code for IA-32 and Intel 64 processors and certain non-Intel but compatible processors, such as certain AMD processors. A specific release of the compiler (11.1) remains available for development of Linux-based applications for IA-64 processors. On Windows, it is known as Intel Visual Fortran. [2]

  8. x86 Bit manipulation instruction set - Wikipedia

    en.wikipedia.org/wiki/X86_Bit_manipulation...

    AMD was the first to introduce the instructions that now form Intel's BMI1 as part of its ABM (Advanced Bit Manipulation) instruction set, then later added support for Intel's new BMI2 instructions. AMD today advertises the availability of these features via Intel's BMI1 and BMI2 cpuflags and instructs programmers to target them accordingly. [2]

  9. Interrupt descriptor table - Wikipedia

    en.wikipedia.org/wiki/Interrupt_descriptor_table

    Software interrupt vector numbers are defined by the specific runtime environment, such as the IBM PC BIOS, DOS, or other operating systems. They are triggered by software using the INT instruction (either by applications, device drivers or even other interrupt handlers).

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