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Despite the halved associativity on the L2 cache, which reduced hit rates compared to the full Coppermine design, it kept the 256-bit wide L2 cache bus, which meant an advantage compared to Mendocino and older Katmai/Pentium II designs, which all had a 64-bit datapath to their L2 caches. [11] [12] SSE instructions were also enabled.
Socket 370 started out as a budget-oriented platform for 66 MHz FSB PPGA Mendocino Celeron CPUs in late 1998, as the move to on-die L2 cache eliminated the need for a PCB design as seen on Slot 1. Socket 370 then became Intel's main desktop socket from late 1999 to late 2000 for 100/133 MHz FSB FC-PGA Coppermine Pentium IIIs.
28 Mendocino (7020 series, Zen2/RDNA2 based) 29 Barcelo-R (7030 series, Zen3/GCN5 based) ... L2 cache: 512 KB per core. All the CPUs support 16 PCIe 3.0 lanes.
L2 cache L3 cache GPU model GPU frequency Power Socket I/O bus Release date sSpec number Part number(s) Release price (USD) Base Max Turbo Standard power: Celeron G6900: 2 (2) 3.4 GHz — 2 × 1.25 MB 4 MB UHD 710: 300–1300 MHz 46 W — LGA 1700: DMI 4.0 ×8: January 2022 SRL67 (H0) CM8071504651805 BX80715G6900 $42 Standard power, embedded ...
Mendocino – 0.25 μm process technology. Introduced August 24, 1998; 242-pin Slot 1 SEPP ... L2 cache is 256 KB, 1 MB, or 2 MB Advanced Transfer Cache (Integrated) ...
2.6.1 Mendocino (7020 series, Zen 2/RDNA2 based) 2.6.2 Barcelo-R ... L2 cache: 1 MB per core. All the CPUs support 20 PCIe 4.0 lanes. Includes integrated RDNA 3 GPU.
Mendocino; Basic Desna, Ontario, Zacate Kabini, Temash Beema, Mullins Carrizo-L ... L2 cache associativity (ways) 16: 8: 16: 8 Max on--die L3 cache per CCX (MiB) ...
Containing 7.5 million transistors (27.4 million in the case of the mobile Dixon with 256 KB on-die L2 cache), the Pentium II featured an improved version of the first P6-generation core of the Pentium Pro, which contained 5.5 million transistors. However, its L2 cache subsystem was a downgrade when compared to the Pentium Pro's.