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A Trusted Platform Module (TPM) is a secure cryptoprocessor that implements the ISO/IEC 11889 standard. Common uses are verifying that the boot process starts from a trusted combination of hardware and software and storing disk encryption keys. A TPM 2.0 implementation is part of the Windows 11 system requirements. [1]
Low Pin Count interface Winbond chip Trusted Platform Module installed on a motherboard, and using the LPC bus. The Low Pin Count (LPC) bus is a computer bus used on IBM-compatible personal computers to connect low-bandwidth devices to the CPU, such as the BIOS ROM (BIOS ROM was moved to the Serial Peripheral Interface (SPI) bus in 2006 [1]), "legacy" I/O devices (integrated into Super I/O ...
The static chain of trust starts when the platform powers on (or the platform is reset), which resets all PCRs to their default value. For server platforms, the first measurement is made by hardware (i.e., the processor) to measure a digitally signed module (called an Authenticated Code Module or ACM) provided by the chipset manufacturer. The ...
Trusted Platform Module, a specification for a secure cryptoprocessor included with some computers; Tivoli Provisioning Manager, a software product by IBM; Trade promotion management, software that supports the management of trade promotion; Technical protection measures, another name for digital rights management
The Intel Classmate PC (a competitor to the One Laptop Per Child) includes a Trusted Platform Module. [53] PrivateCore vCage software can be used to attest x86 servers with TPM chips. Mobile T6 secure operating system simulates the TPM functionality in mobile devices using the ARM TrustZone technology. [54]
When used in conjunction with a compatible Trusted Platform Module (TPM), BitLocker can validate the integrity of boot and system files before decrypting a protected volume; an unsuccessful validation will prohibit access to a protected system. [6] [7] BitLocker was briefly called Secure Startup before Windows Vista's release to manufacturing. [6]
Quad SPI (QSPI; different to but has same abbreviation as Queued-SPI described in § Intelligent SPI controllers) goes beyond dual SPI, adding two more I/O lines (SIO2 and SIO3) and sends 4 data bits per clock cycle. Again, it is requested by special commands, which enable quad mode after the command itself is sent in single mode.
The PSP is an integral part of the boot process, without which the x86 cores would never be activated. On-chip phase Firmware located directly on the PSP chip sets up the ARM CPU, verifies the integrity of the SPI ROM, using various data structures locates the off-chip firmware (AGESA) from the SPI ROM, and copies it over to internal PSP memory.
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