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a6-3400m: 2011 6/14 4 (4) 1.4 2.3 4× 1mb hd 6520g 320:16:8 400 256 35 am3400ddx43gx a6-3410mx: 1.6 1600 45 am3410hlx43gx a6-3420m: december 7, 2011 1.5 2.4 1333 35 am3420ddx43gx a6-3430mx: 1.7 1600 45 am3430hlx43gx a8-3500m: 2011 6/14 1.5 2.4 hd 6620g 400:20:8 444 355.2 1333 35 am3500ddx43gx a8-3510mx: 1.8 2.5 1600 45 am3510hlx43gx a8-3520m ...
Architecture Fabrication (nm) Family Release Date Code name Model Group Cores SMT Clock rate () Bus Speed & Type [a] Cache Socket Memory Controller Features L1 L2
The Puma Family 16h is a low-power microarchitecture by AMD for its APUs. ... A6 Micro 6500T 1.8 Radeon R4 401 A4 Micro 6400T 1.0 1.6 Radeon R3 350 E1 Micro
AMD announced the Brazos-T platform on 9 October 2012. It comprised the 4.5-watt AMD Z-Series APU (codenamed Hondo) and the A55T Fusion Controller Hub (FCH), designed for the tablet computer market. [42] [43] The Hondo APU is a redesign of the Desna APU. AMD lowered energy use by optimizing the APU and FCH for tablet computers. [44] [45]
The XOP (eXtended Operations [1]) instruction set, announced by AMD on May 1, 2009, is an extension to the 128-bit SSE core instructions in the x86 and AMD64 instruction set for the Bulldozer processor core, which was released on October 12, 2011. [2] However AMD removed support for XOP from Zen (microarchitecture) onward. [3]
The AMD K6 microprocessor is the 2nd generation of x86-compatible 32-bit processors designed by AMD. The K6 core was derived from the NexGen Nx686 core being developed based on the RISC86 architecture.
Unified Video Decoder (UVD, previously called Universal Video Decoder) is the name given to AMD's dedicated video decoding ASIC. There are multiple versions implementing a multitude of video codecs, such as H.264 and VC-1. UVD was introduced with the Radeon HD 2000 Series and is integrated into some of AMD's GPUs and APUs.