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2. Wafer-level packaging - Wikipedia

   en.wikipedia.org/wiki/Wafer-level_packaging

   A wafer-level package attached to a printed-circuit board. Wafer-level packaging (WLP) is a process in integrated circuit manufacturing where packaging components are attached to an integrated circuit (IC) before the wafer – on which the IC is fabricated – is diced. In WLP, the top and bottom layers of the packaging and the solder bumps are ...

3. Embedded wafer level ball grid array - Wikipedia

   en.wikipedia.org/wiki/Embedded_Wafer_Level_Ball...

   Embedded wafer level ball grid array (eWLB) is a packaging technology for integrated circuits. The package interconnects are applied on an artificial wafer made of silicon chips and a casting compound. Principle eWLB. eWLB is a further development of the classical wafer level ball grid array technology (WLB or WLP: wafer level package). The ...

4. Fan-out wafer-level packaging - Wikipedia

   en.wikipedia.org/wiki/Fan-out_wafer-level_packaging

   This is known as a chip-first flow. Panel level packaging uses a large panel instead of a wafer to carry out the packaging process. [6] High end fan-out packages are those with lines and spaces narrower than 8 microns. [4] Fan-out packages can also have several dies, [5] and passive components. [6]

5. Through-silicon via - Wikipedia

   en.wikipedia.org/wiki/Through-silicon_via

   It was a variation of the TSV process, and was later called SLID (solid liquid inter-diffusion) technology. [18] The term "through-silicon via" (TSV) was coined by Tru-Si Technologies researchers Sergey Savastiouk, O. Siniaguine, and E. Korczynski, who proposed a TSV method for a 3D wafer-level packaging (WLP) solution in 2000. [19]

6. List of electronic component packaging types - Wikipedia

   en.wikipedia.org/wiki/List_of_electronic...

   Fan-out wafer-level packaging: Variation of WLCSP. Like a BGA package but with the interposer built directly atop the die and encapsulated alongside it. eWLB: Embedded wafer level ball grid array: Variation of WLCSP. MICRO SMD-Chip-size package (CSP) developed by National Semiconductor [21] COB: Chip on board: Bare die supplied without a package.

7. Advanced packaging (semiconductors) - Wikipedia

   en.wikipedia.org/wiki/Advanced_packaging...

   Advanced packaging includes multi-chip modules, 3D ICs, [2] 2.5D ICs, [2] heterogeneous integration, [3] fan-out wafer-level packaging, [2] system-in-package, quilt packaging, combining logic (processors) and memory in a single package, die stacking, wafer bonding/stacking, several chiplets or dies in a package, [2] combinations of these ...

8. Glossary of microelectronics manufacturing terms - Wikipedia

   en.wikipedia.org/wiki/Glossary_of...

   wafer-to-wafer (also wafer-on-wafer) stacking – bonding and integrating whole processed wafers atop one another before dicing the stack into dies; wire bonding – using tiny wires to interconnect an IC or other semiconductor device with its package (see also thermocompression bonding, flip chip, hybrid bonding, etc.) WLP – see wafer-level ...

9. Three-dimensional integrated circuit - Wikipedia

   en.wikipedia.org/wiki/Three-dimensional...

   3D packaging refers to 3D integration schemes that rely on traditional interconnection methods such as wire bonding and flip chip to achieve vertical stacking. 3D packaging can be divided into 3D system in package (3D SiP) and 3D wafer level package (3D WLP). 3D SiPs that have been in mainstream manufacturing for some time and have a well ...