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Intel Celeron Mendocino 300 MHz in SEPP package Top of a Mendocino-core Socket 370 Celeron (PPGA package) Underside of a Mendocino-core Socket 370 Celeron, 333 MHz Intel Celeron 500MHz Mendocino die shot. The Mendocino Celeron, launched August 24, 1998, was the first retail CPU to use on-die L2 cache. Whereas Covington had no secondary cache at ...
The latest standard badge design used by Intel to promote the Celeron brand. The Celeron was a family of microprocessors from Intel targeted at the low-end consumer market. . CPUs in the Celeron brand have used designs from sixth- to eighth-generation CPU microarchitectur
Socket 370 started out as a budget-oriented platform for 66 MHz FSB PPGA Mendocino Celeron CPUs in late 1998, as the move to on-die L2 cache eliminated the need for a PCB design as seen on Slot 1. Socket 370 then became Intel's main desktop socket from late 1999 to late 2000 for 100/133 MHz FSB FC-PGA Coppermine Pentium IIIs.
Intel Core Duo T2300 1.66 GHz; Intel Core Duo T2050 1.6 GHz; Intel Core Duo T2300e 1.66 GHz; Intel Core Duo T2080 1.73 GHz; Intel Core Duo L2500 1.83 GHz (low voltage, 15 W TDP) Intel Core Duo L2400 1.66 GHz (low voltage, 15 W TDP) Intel Core Duo L2300 1.5 GHz (low voltage, 15 W TDP) Intel Core Duo U2500 1.2 GHz (ultra-low voltage, 9 W TDP)
Core i7, on the desktop platform no longer supports hyper-threading; instead, now higher-performing core i9s will support hyper-threading on both mobile and desktop platforms. Before 2007 and post-Kaby Lake, some Intel Pentium and Intel Atom (e.g. N270, N450) processors support hyper-threading. Celeron processors never supported it.
Willamette core only. Can accept some of Socket 478 CPU with an adapter Socket 495: 2000 Intel Celeron Intel Pentium III: Notebook PGA: 495 1.27 [3] 66–133 MHz Socket 603: 2001 Intel Xeon: Server PGA: 603 1.27 [4] 100–133 MHz 400–533 MT/s Socket 478/ Socket N: 2001 Intel Pentium 4 Intel Celeron Intel Pentium 4 EE Intel Pentium 4 M ...
Socket 370 was initially made for low-cost Celeron processors starting with the Mendocino Celerons, while Slot 1 was thought of as a platform for the more expensive Pentium II and early Pentium III models. Both cache and core were embedded into the die.
A common overclock involved the pin-40 hack, or using an ABIT BP6 or Asus P2B, and setting the bus speed on a 66 MHz Covington or Mendocino-core Celeron to 100 MHz. The Mendocino-core Celeron 300A became a "sweet spot" for overclockers, with nearly 100% success rates at reaching 450 MHz on a 100 MHz FSB, allowing it to equate to a much more ...